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For a pipelined CPU with a single ALU, consider the following situations

1. The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand

2. The execution of a conditional jump instruction

3. The $j^{th}$ and ${j+1}^{st}$ instructions require the ALU at the same time.

Which of the above can cause a hazard

1. I and II only
2. II and III only
3. III only
4. All the three
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1. Data hazard
2. Control hazard
3. Structural hazard as only one ALU is there

So, D all of these.

http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html

selected
Hazards in pipelining occur due to sync ,interrupts,branching,raw timings and all three have one or the other problem so they shouldnt be pipelined option d.