edited by
9,408 views
30 votes
30 votes

For a pipelined CPU with a single ALU, consider the following situations

  1. The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand

  2. The execution of a conditional jump instruction

  3. The $j^{th}$ and ${j+1}^{st}$ instructions require the ALU at the same time.

Which of the above can cause a hazard

  1. I and II only
  2. II and III only
  3. III only
  4. All the three
edited by

5 Answers

–2 votes
–2 votes
Hazards in pipelining occur due to sync ,interrupts,branching,raw timings and all three have one or the other problem so they shouldnt be pipelined option d.
Answer:

Related questions

33 votes
33 votes
4 answers
1
Kathleen asked Sep 17, 2014
12,022 views
Consider the following system of linear equations $$\left( \begin{array}{ccc} 2 & 1 & -4 \\ 4 & 3 & -12 \\ 1 & 2 & -8 \end{array} \right) \left( \begin{array}{ccc} x \\ y...
35 votes
35 votes
3 answers
3
Kathleen asked Sep 17, 2014
14,990 views
Consider the following assembly language program for a hypothetical processor $A, B,$ and $C$ are $8-$bit registers. The meanings of various instructions are shown as com...