30 votes 30 votes For a pipelined CPU with a single ALU, consider the following situations The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand The execution of a conditional jump instruction The $j^{th}$ and ${j+1}^{st}$ instructions require the ALU at the same time. Which of the above can cause a hazard I and II only II and III only III only All the three CO and Architecture gatecse-2003 co-and-architecture pipelining normal isrodec2017 + – Kathleen asked Sep 16, 2014 edited Dec 26, 2017 by pavan singh Kathleen 9.4k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
–2 votes –2 votes Hazards in pipelining occur due to sync ,interrupts,branching,raw timings and all three have one or the other problem so they shouldnt be pipelined option d. anshu answered Feb 3, 2015 anshu comment Share Follow See all 0 reply Please log in or register to add a comment.