Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
Now to MULTIPLY these two Numbers:
For $4$ bits, Total Delay$= 3+4=7$
For $n$ bits, Total Delay$=n-1+n = 2n-1$
So, Total Delay $=\Theta(n).$
@VS ji. Thanks for valuable effort. Just small addition if look ahead carry adder is used then 4-Unit of delay in each adder. But it will not change answer because 4 is a constant with respect to n.
16 AND gates are used, but in the calculation 4 are considered...is it because every time 4 AND gates will work simultaneously? (Like for multiplication of B0 with A3A2A1A0, the AND gates used work simultaneously and so the total delay is 1?)
Diagramatic answer seems to helpful. But still dont know how to drive the equation "So the delay is approxiamtely sqrt(2)*(2n-1)."
if Td = Θ(1) , then the total delay of multiplexer is Θ(n)
worst case delay would be (2n+1)td .where td is the time delay of gates. , is it correct ???
Sir I have ordered GO PDF on 16 Aug 2018 still ...