MadeEasy Test Series: CO & Architecture - Cache Memory

Question

Question :

Comments

I think some miss in question.

Without memory line size, how can we calculate it?

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block sizes are same on MM and cache @srestha ?

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0.1 ( read + write )

0.1(0.75*168*1 + 0.25*168*2 + 32*1) = 25 * 8 B

but if it is write through then why do we need dirty bits ?

is it right ? please let me know.

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@gatesjt because question is made by ME

Answer 1

21 for read as 32 for write.total  53

Answer 2

For read, memory references:   168 (0.9(0) + 0.1(1) )  = 16.8

For write, memory refernces :   32 (0.9(1) + 0.1(1) ) = 32

Total memory references, interms of bytes = (16.8 + 32)*128 = 6246.4 ~ 6246

As one line has 128 Bytes

Since write through is used , there is no need to consider dirty bits.

Comments

in case of miss ... missing mem block should be brought into cache first right ?

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yes, that is why the 0.25 term is there

and it will also be included in write as you have to bring the block just written in memory to cache, because it is what cache is meant for, to contain recently accessed blocks.

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If a word is missing in cache, then corresponding entire block 128B request is made to MainMem and brought into cache.I terms of time we add only Main Mem penalty for that transfer (Tm) .why ? because all those 128B will be parallely accessed from Main Memory for which overall latency is Tm only. That's why we write  missrate*(Tm+Tc+etc..) in a cache miss situation to calculate TIME

That being said, my question is are you counting memory reference in terms ok blocks ? Because they are asking in terms of bytes..please complete it in terms of Byte.

Further..

This is not related to your solution.

When you write on a hit in cache, you considered write through to lower level , ( you given it as 0.9*1 block) . So, whenever you make something dirty in cache, It can be remain dirty. Lower and upper both levels remains same in terms of data,because of write through policy implementation. Then why there is again possibility of 0.25 dirty ?

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@Debashish yes, you are right. Since write through is used no need to use dirty bits. I have edited the answer.

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Why did u consider the 0unit when there is a hit for Read and 1unit when there is a miss for Read?

Similarly, 1unit when there is hit for write and 1unit when there is miss for write. Why so?

Answer 3

There is no use of dirty bit.

168 read out of which 10% needs memory access. 17 memory accesses for read.

32 write instructions. in case of cache miss we need 4 memory access. Because cache is write through we need 32 more memory acess for writing.

Total = 17 + 4 + 32 = 53

Comments

"dirty bits" should not have been in the question.

But why "4" extra for write case as all accesses are anyway going to memory? And final answer is asked in bytes - not words.