Cache Coherence

Question

Given a virtual memory system with a TLB, a cache, and a page table, assume the following:

•A TLB hit requires 5ns.

•A cache hit requires 12ns.

•A memory reference requires 25ns. •

A disk reference requires 200ms (this includes updating the page table, cache, and TLB). •

The TLB hit ratio is 90%. • The cache hit rate is 98%. • The page fault rate is .001%. •

 On a TLB or cache miss, the time required for access includes a TLB and/or cache update, but the access is not restarted. • On a page fault, the page is fetched from disk, all updates are performed, but the access is restarted. • All references are sequential (no overlap, nothing done in parallel).

For each of the following, indicate whether or not it is possible. If it is possible, speciify the time required for accessing the requested data. a) TLB hit, cache hit b) TLB miss, page table hit, cache hit c) TLB miss, page table hit, cache miss d) TLB miss, page table miss, cache hit e) TLB miss, page table miss Write down the equation to calculate the effective access time.

please help and what we do mean by access is not restarted in above .

Comments

The question title is misleading. This problem is not related to cache coherence.

Answer 1

It is not directly mentioned, but it is clear that we are talking about a physically indexed cache (cache after address translation)

a. TLB hit, cache hit:

5 + 12 = 17 ns

b. TLB miss, page table hit, cache hit

5 + 25 + 12 = 42 ns (when TLB misses, page table which is in main memory is accessed)

c) TLB miss, page table hit, cache miss

5 + 25 + 12 + 25 = 67 ns

d) TLB miss, page table miss, cache hit

When page table misses, cache hit cannot happen. Because when a page fault happens, we shouldn't check the cache as it won't be having the requested data. At this point page fault service routine must be instantiated.

e) TLB miss, page table miss

5 + 25 + 200 + 5 + 12 = 247 ns

It is mentioned in question that access is restarted on a page fault. So, once page is fetched, there will be another page request which will hit in TLB and also in cache.

$EAT = 0.9 \left(5 + \underbrace{0.98 \times 12}_{\text{cache hit}}+\underbrace{0.02 \left(12+25\right)}_{\text{cache miss}}\right) \text{(TLB hit)} \\+ 0.1 \left(5 + 0.999 \left(25 + \underbrace{0.98 \times 12}_{\text{cache hit}} +\underbrace{0.02\left(12+25\right)}_{\text{cache miss}}\right)\right)\text{(TLB miss, page hit)} \\ +0.1\left(5+ 0.001 \left(25+200+\underbrace{5+12}_{\text{access restarted}}\right)\right)\text{(TLB miss, page fault)}$

Comments

In the EAT the TLB Mss and page fault section whether with the 200ms we require to add 5+12 ns? because the access is restarted once again.