0 votes 0 votes closed as a duplicate of: MadeEasy Test Series: CO & Architecture - Cache Memory I am not understanding how options are given because even when one miss will occur entire cache block will be accessed, so 128 B will be accessed. CO and Architecture cache-memory co-and-architecture write-through + – Rahul Jain25 asked Dec 9, 2016 retagged Mar 15, 2019 by Naveen Kumar 3 Rahul Jain25 325 views comment Share Follow See all 0 reply Please log in or register to add a comment.