# GATE1988-2-ii

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Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer.
$$\begin{array}{ll} \text{14} & \text{double address instructions} \\ \text{127} & \text{single address instructions} \\ \text{60} & \text{no address (zero address) instructions} \\ \end{array}$$
$$\require {multicolumn} \begin{array}{|c|c|c|} \leftarrow4\text{ bits}\rightarrow& \leftarrow6\text{ bits}\rightarrow & \leftarrow6\text{ bits}\rightarrow \\ \hline \text{Opcode}& \underset{\text{Address}}{\text{Operand 1}}& \underset{\text{Address}}{\text{Operand 2}} \\\hline \end{array}$$

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@Arjun sir

I have a doubt that here 14 double address instructions mean that 14 operations(opcodes) ?

Is saying that there is an instruction same as saying that there is an operation?

$4$ bits are for the opcode so number of $2$ address instructions will be $2^4 =16-$ so $14$ double instructions are possible.

But out of $16$ only $14$ are used so $2$ are still left which can be used for $1$ address instruction. For $1$ address instruction we can use not only the $2$ left over but also the $6$ bits of operand $1$ (to make it one address) $-$ so $6$ bits that is $64.$ So, total $2\times 64$ single address instructions can be supported $-$ So, $127$ single instructions are possible

But out of $128,127$ are used so $1$ left which can be used for zero-address instruction. To make number of zero address we can use the operand $2$ address (we already included operand 1 address)  $- 6$ bits. So, total number possible is $64.$ So,
total $1\times 64 = 64$ zero address instructions are possible.

So, all encoding are possible.

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they all b at a time ?
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So initally there is instruction  of 16 bit

where 4 bit for opcode and two 6 bit for operand 1 and 2 respectively .

Now they ask it is possible to get

so we assume that we can do it by taking 4 bit of previous so total 16 bit possible .

I don't get thiz But out of 16 only 14 are used so 2 are still left which can be used for 1 address instruction

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we will take whole bit so how can we further break it?It is like select line na?
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yeah two are left in all the possible 4 bit encodings
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This is slightly incorrect.

Let us use 0000 to 1101 (I am talking about the MSB bits) and the rest can be used for operands So, there 14 double address instructions are possible.

Now, we have two patterns left from the first four bits - 1110 and 1111.
With the first, we can have 64 1 address instructions and with the second, we can have 63 instructions.

Why only 63 for the second? Because we reserve one pattern to help us identify 0 address codes i.e the last one address code possible will be 1111 111110.

Now for 0 address code, they'll start with 1111 111111 and we have 6 bits left - giving us 64 instructions.

Hence, all of them are possible.
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Thank you for the clear explanation @Gokulnath

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In the question it says, that 4 bits are available for opcode. Now,in the answer it is said "But out of 128,127 are used so 1 is  left which can be used for zero-address instruction", so for the one combination that is used for the zero-address instructions the 4 opcode bits will be the same as, the other 63 combinations used for 1 address instruction.

How will CU differntiate between these instructions if opcode bits are same? CU decides the type of instruction by looking ar the opcode bits , am I wrong?
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watch this video . all doubts will be resolved.

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expanding opcodes is very well explained in their NPTEL lectures by IIT Madras, Professor V Kamakoti

There are 14 two-address instructions which consume 14*26*26 =  combinations

There are 127 one-address instructions which consume 127*26 =  combinations

There are 60 zero-address instructions which consume 60 combinations

Total number of combinations consumed = 57344 + 8128 + 60 = 65532

We have a total of 216 = 65536 combinations  which is >65532

So it is possible to encode all these instructions using the given instructions format ... Infact we will have 4 extra combinations ...

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