shift register output

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AND gate o/p is 1 if both i/p are 1.

Now see AND gate i/p's are clock signal  and Q1'.

AND gate o/p acts as clock,to shift register.

clock pulse 1 AND Q1' =>1 and 1 =>shift register shifts => we get 0110

Now nothing happens because input to AND gate is 0 (Q1').

clock is controlled by AND gate.