Computing Effective Memory access time - Cache organization

Question

Consider the following information about a hypothetical processor.

Assume the cache is physically addressed

TLBHit Rate: 95% access time 1 cycle

Cache Hit Rate: 90% access time 1 cycle

when tlb and cache both get miss, page fault rate 1%

TLB access and cache access are sequential. Main Memory access time 5 cycles. Hard disk 100 cycles.

Page table is always kept in main memory. Compute average memory access time?

Ans Given : 3 cycles

My approach:

MAT= Time for VA->PA translation + data access

= tlb_access + tlb_miss*( cache_access + cache_miss*(MainMem) ) + cache_access + cachemiss*( mainmemory +  page_fault*( HardDisk) )

= 1 + .05(1+.1(5)) + 1 + .1(5+ .01(100) ) = 2.675

Could  someone pls point out the flaw in the logic?

Answer 1

Formula would be = tlb_access + tlb_miss*( cache_miss*(MainMem) ) + cachemiss*( mainmemory + page_fault*( HardDisk) ) , now calculate.

TLB access and cache access are sequential, is given ..so cache access time is not require again ..

Comments

Hello Bikram, Do we have any document or link supporting this formula ?

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I see this problem, according to problem this formula came..what conditions given in question based on that it is derived.

No such fixed formula .

You may check Stallings for it .