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0 votes
3 answers
1
primary key for an entity
A primary key for an entity is a candidate key any attribute a unique attribute a superkey
A primary key for an entity is a candidate key any attribute a unique attribute a superkey
comment edited 42 minutes ago in Databases Sanjay Sharma 1.2k views
63 votes
7 answers
2
GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ ... ? $2 \hspace{0.1cm} nanoseconds$ $20 \hspace{0.1cm} nanoseconds$ $22 \hspace{0.1cm}nanoseconds$ $88 \hspace{0.1cm} nanoseconds$
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2 \hspace{0.1cm} nanoseconds$ ... this transfer? $2 \hspace{0.1cm} nanoseconds$ $20 \hspace{0.1cm} nanoseconds$ $22 \hspace{0.1cm}nanoseconds$ $88 \hspace{0.1cm} nanoseconds$
answered 49 minutes ago in CO and Architecture sahil tron 21.6k views
36 votes
4 answers
3
GATE CSE 2016 Set 1 | Question: 29
Consider the following experiment. Step 1. Flip a fair coin twice. Step 2. If the outcomes are (TAILS, HEADS) then output $Y$ and stop. Step 3. If the outcomes are either (HEADS, HEADS) or (HEADS, TAILS), then output $N$ and stop. Step 4. ... (TAILS, TAILS), then go to Step 1. The probability that the output of the experiment is $Y$ is (up to two decimal places)
Consider the following experiment. Step 1. Flip a fair coin twice. Step 2. If the outcomes are (TAILS, HEADS) then output $Y$ and stop. Step 3. If the outcomes are either (HEADS, HEADS) or (HEADS, TAILS), then output $N$ and stop. Step 4. If the outcomes are (TAILS, TAILS), then go to Step 1. The probability that the output of the experiment is $Y$ is (up to two decimal places)
commented 1 hour ago in Probability gurichouhan 6.5k views
1 vote
4 answers
4
transaction cascadeless
is this is cascadeless? r1(X),w2(X),w1(X), abort2, commit1
is this is cascadeless? r1(X),w2(X),w1(X), abort2, commit1
answered 2 hours ago in Databases rishabhgupta12 489 views
3 votes
1 answer
5
GATE1987-9f
Give the composition tables (Cayley Tables) of the two non-isomorphic groups of order $4$ with elements $e, a, b, c$ where $c$ is the identity element. Use the order $e, a, b, c$ for the rows and columns.
Give the composition tables (Cayley Tables) of the two non-isomorphic groups of order $4$ with elements $e, a, b, c$ where $c$ is the identity element. Use the order $e, a, b, c$ for the rows and columns.
retagged 3 hours ago in Set Theory & Algebra Lakshman Patel RJIT 313 views
23 votes
1 answer
6
Gate1987-1-vi
Microprogrammed control unit: is faster than a hardwired control unit facilitates easy implementation of new instructions is useful when very small programs are to be run usually refers to control unit of a microprocessor
Microprogrammed control unit: is faster than a hardwired control unit facilitates easy implementation of new instructions is useful when very small programs are to be run usually refers to control unit of a microprocessor
edited 3 hours ago in CO and Architecture Lakshman Patel RJIT 6.6k views
4 votes
1 answer
7
GATE1987-9d
Specify an adjacency-lists representation of the undirected graph given above.
Specify an adjacency-lists representation of the undirected graph given above.
answer edited 3 hours ago in Graph Theory Lakshman Patel RJIT 779 views
1 vote
0 answers
8
GATE1987-5a
Eight $7$-segment LED displays and a keyboard consisting of $28$ keys are to be interfaced to a microprocessor based system. Give the block diagram of the interface circuit using minimum number of port lines from any programmable I/O chip. Use any other IC chip if necessary.
Eight $7$-segment LED displays and a keyboard consisting of $28$ keys are to be interfaced to a microprocessor based system. Give the block diagram of the interface circuit using minimum number of port lines from any programmable I/O chip. Use any other IC chip if necessary.
retagged 3 hours ago in CO and Architecture Lakshman Patel RJIT 175 views
2 votes
1 answer
9
GATE1987-4c
Give the character format for data transmission in asynchronous serial mode.
Give the character format for data transmission in asynchronous serial mode.
retagged 3 hours ago in Computer Networks Lakshman Patel RJIT 361 views
1 vote
0 answers
10
GATE1987-3a
Design an $8 \times 8$ multiplier using five $4$-bits adders and $4$ ROM's each programmed to realise $4 \times 4$ multiplier.
Design an $8 \times 8$ multiplier using five $4$-bits adders and $4$ ROM's each programmed to realise $4 \times 4$ multiplier.
retagged 3 hours ago in Digital Logic Lakshman Patel RJIT 287 views
18 votes
3 answers
11
GATE1987-2k
State whether the following statements are TRUE or FALSE: The intersection of two CFL's is also a CFL.
State whether the following statements are TRUE or FALSE: The intersection of two CFL's is also a CFL.
answer edited 3 hours ago in Theory of Computation Lakshman Patel RJIT 1.4k views
2 votes
2 answers
12
GATE1987-2f
State whether the following statements are TRUE or FALSE: Every infinite cyclic group is isomorphic to the infinite cyclic group of integers under addition.
State whether the following statements are TRUE or FALSE: Every infinite cyclic group is isomorphic to the infinite cyclic group of integers under addition.
edited 3 hours ago in Graph Theory Lakshman Patel RJIT 521 views
3 votes
1 answer
13
GATE1987-2e
State whether the following statement is TRUE or FALSE: There is a linear-time algorithm for testing the planarity of finite graphs.
State whether the following statement is TRUE or FALSE: There is a linear-time algorithm for testing the planarity of finite graphs.
retagged 3 hours ago in Graph Theory Lakshman Patel RJIT 617 views
16 votes
4 answers
14
GATE1987-16-a
A Boolean function $f$ is to be realized only by $\text{NOR}$ gates. Its $K$-map is given below: The realization is
A Boolean function $f$ is to be realized only by $\text{NOR}$ gates. Its $K$-map is given below: The realization is
answer edited 3 hours ago in Digital Logic Lakshman Patel RJIT 1.9k views
15 votes
3 answers
15
GATE1987-13-a
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three clock pulses are also given. State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$ Initial $1$ $1$ $1$ $1$ After ... $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three clock pulses are also given. State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$ Initial $1$ $1$ $1$ $1$ After the first ... $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$
retagged 3 hours ago in Digital Logic Lakshman Patel RJIT 1.5k views
1 vote
2 answers
16
GATE1987-11c
The relative costs of assigning jobs $J_{1}, J_{2}$ and $J_{3}$ to machines $M_{1}, M_{2}$ and $M_{3}$ are given below: $\begin{array}{|c|cccc|}\hline\textbf{JOBS} && \textbf{Machines} \\ & \textbf{$ ... Using the assignment method find the assignment involving minimum cost. Is this an optimal assignment?
The relative costs of assigning jobs $J_{1}, J_{2}$ and $J_{3}$ to machines $M_{1}, M_{2}$ and $M_{3}$ are given below: $\begin{array}{|c|cccc|}\hline\textbf{JOBS} && \textbf{Machines} \\ & \textbf{$M_{1}$} & \textbf{$M_{2}$} & \textbf{$ ... Using the assignment method find the assignment involving minimum cost. Is this an optimal assignment?
retagged 3 hours ago in Algorithms Lakshman Patel RJIT 582 views
17 votes
6 answers
17
GATE1987-10d
Give a regular expression over the alphabet $\{0, 1\}$ to denote the set of proper non-null substrings of the string $0110$.
Give a regular expression over the alphabet $\{0, 1\}$ to denote the set of proper non-null substrings of the string $0110$.
answer edited 3 hours ago in Theory of Computation Lakshman Patel RJIT 2.5k views
28 votes
6 answers
18
GATE1987-10b
What is the generating function $G(z)$ for the sequence of Fibonacci numbers?
What is the generating function $G(z)$ for the sequence of Fibonacci numbers?
answer edited 3 hours ago in Combinatory Lakshman Patel RJIT 4.5k views
9 votes
1 answer
19
GATE1987-1-xxvi
If $f(x_{i}).f(x_{i+1})< 0$ then There must be a root of $f(x)$ between $x_i$ and $x_{i+1}$ There need not be a root of $f(x)$ between $x_{i}$ and $x_{i+1}$ There fourth derivative of $f(x)$ with respect to $x$ vanishes at $x_{i}$ The fourth derivative of $f(x)$ with respect to $x$ vanishes at $x_{i+1}$
If $f(x_{i}).f(x_{i+1})< 0$ then There must be a root of $f(x)$ between $x_i$ and $x_{i+1}$ There need not be a root of $f(x)$ between $x_{i}$ and $x_{i+1}$ There fourth derivative of $f(x)$ with respect to $x$ vanishes at $x_{i}$ The fourth derivative of $f(x)$ with respect to $x$ vanishes at $x_{i+1}$
answer edited 4 hours ago in Calculus Lakshman Patel RJIT 1.1k views
1 vote
0 answers
20
GATE1987-1-xxiv
The simplex method is so named because It is simple. It is based on the theory of algebraic complexes. The simple pendulum works on this method. No one thought of a better name.
The simplex method is so named because It is simple. It is based on the theory of algebraic complexes. The simple pendulum works on this method. No one thought of a better name.
retagged 4 hours ago in Numerical Methods Lakshman Patel RJIT 261 views
13 votes
5 answers
21
GATE1987-1-xxii
The equation $7x^{7}+14x^{6}+12x^{5}+3x^{4}+12x^{3}+10x^{2}+5x+7=0$ has All complex roots At least one real root Four pairs of imaginary roots None of the above
The equation $7x^{7}+14x^{6}+12x^{5}+3x^{4}+12x^{3}+10x^{2}+5x+7=0$ has All complex roots At least one real root Four pairs of imaginary roots None of the above
answer edited 4 hours ago in Set Theory & Algebra Lakshman Patel RJIT 1k views
12 votes
4 answers
22
GATE1987-1-xxi
If $a, b,$ and $c$ are constants, which of the following is a linear inequality? $ax+bcy=0$ $ax^{2}+cy^{2}=21$ $abx+a^{2}y \geq 15$ $xy+ax \geq 20$
If $a, b,$ and $c$ are constants, which of the following is a linear inequality? $ax+bcy=0$ $ax^{2}+cy^{2}=21$ $abx+a^{2}y \geq 15$ $xy+ax \geq 20$
answer edited 4 hours ago in Linear Algebra Lakshman Patel RJIT 1.8k views
34 votes
6 answers
23
GATE1987-1-xviii
Let $P$ be a quicksort program to sort numbers in ascending order. Let $t_{1}$ and $t_{2}$ be the time taken by the program for the inputs $\left[1 \ 2 \ 3 \ 4\right]$ and $\left[5 \ 4 \ 3 \ 2 \ 1\right]$, respectively. Which of the following holds? $t_{1} = t_{2}$ $t_{1} > t_{2}$ $t_{1} < t_{2}$ $t_{1}=t_{2}+5 \log 5$
Let $P$ be a quicksort program to sort numbers in ascending order. Let $t_{1}$ and $t_{2}$ be the time taken by the program for the inputs $\left[1 \ 2 \ 3 \ 4\right]$ and $\left[5 \ 4 \ 3 \ 2 \ 1\right]$, respectively. Which of the following holds? $t_{1} = t_{2}$ $t_{1} > t_{2}$ $t_{1} < t_{2}$ $t_{1}=t_{2}+5 \log 5$
answer edited 4 hours ago in Algorithms Lakshman Patel RJIT 6.8k views
16 votes
1 answer
24
GATE1987-1-xvi
A critical region is One which is enclosed by a pair of $P$ and $V$ operations on semaphores. A program segment that has not been proved bug-free. A program segment that often causes unexpected system crashes. A program segment where shared resources are accessed.
A critical region is One which is enclosed by a pair of $P$ and $V$ operations on semaphores. A program segment that has not been proved bug-free. A program segment that often causes unexpected system crashes. A program segment where shared resources are accessed.
answer edited 4 hours ago in Operating System Lakshman Patel RJIT 2k views
15 votes
3 answers
25
GATE1987-1-xv
In a circular linked list oraganisation, insertion of a record involves modification of One pointer. Two pointers. Multiple pointers. No pointer.
In a circular linked list oraganisation, insertion of a record involves modification of One pointer. Two pointers. Multiple pointers. No pointer.
answer edited 4 hours ago in DS Lakshman Patel RJIT 7.4k views
13 votes
4 answers
26
GATE1987-1-xiv
An operator precedence parser is a Bottom-up parser. Top-down parser. Back tracking parser. None of the above.
An operator precedence parser is a Bottom-up parser. Top-down parser. Back tracking parser. None of the above.
answer edited 4 hours ago in Compiler Design Lakshman Patel RJIT 1.7k views
12 votes
3 answers
27
GATE1987-1-xiii
FORTRAN is a: Regular language. Context-free language. Context-senstive language. None of the above.
FORTRAN is a: Regular language. Context-free language. Context-senstive language. None of the above.
answer edited 4 hours ago in Theory of Computation Lakshman Patel RJIT 3.4k views
17 votes
2 answers
28
GATE1987-1-xii
A context-free grammar is ambiguous if: The grammar contains useless non-terminals. It produces more than one parse tree for some sentence. Some production has two non terminals side by side on the right-hand side. None of the above.
A context-free grammar is ambiguous if: The grammar contains useless non-terminals. It produces more than one parse tree for some sentence. Some production has two non terminals side by side on the right-hand side. None of the above.
answer edited 4 hours ago in Theory of Computation Lakshman Patel RJIT 4.9k views
2 votes
1 answer
29
GATE1987-1-x
The data transfer rate of a double-density floppy disk system is about: $5K$ bits/sec $50K$ bits/sec $500K$ bits/sec $5000K$ bits/sec
The data transfer rate of a double-density floppy disk system is about: $5K$ bits/sec $50K$ bits/sec $500K$ bits/sec $5000K$ bits/sec
retagged 4 hours ago in Computer Peripherals Lakshman Patel RJIT 508 views
1 vote
1 answer
30
GATE1987-1-ix
The refreshing rate of dynamic RAMs is in the range of $2$ microseconds $2$ milliseconds. $50$ milliseconds $500$ milliseconds
The refreshing rate of dynamic RAMs is in the range of $2$ microseconds $2$ milliseconds. $50$ milliseconds $500$ milliseconds
retagged 4 hours ago in CO and Architecture Lakshman Patel RJIT 1.1k views
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