Recent activity in CO and Architecture / GATE Overflow for GATE CSE

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COA : Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be active anytime. The micro instruction of the control unit stores control signal information ... 12 bits address field. The size of the control memory required is? I am not able to solve this question please help

Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be acti...

Shubham Sharma 2

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Shubham Sharma 2 retagged 2 hours ago

97 votes

10 answers

2

GATE CSE 2013 | Question: 45
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

Consider an instruction pipeline with five stages without any branch prediction:Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (...

Sun Wukong

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Sun Wukong answered 1 day ago

1 votes

2 answers

3

Control Unit
Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Each micro instruction contains 3 fields: 118 control signals to support horizontal control unit, a MUX select field to select one of 8 inputs, and a next address field. The size of control memory needed is?

Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Eac...

Psy Duck

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Psy Duck answered Apr 5

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1 answer

4

Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be active anytime. The micro instruction of the control unit stores control signal information along with 3-bit MUX select and 12 bits address field. The size of the control memory required is?

Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be acti...

Akshit690

226 views

Akshit690 commented Apr 5

75 votes

8 answers

5

GATE CSE 2016 Set 2 | Question: 33
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac...

nilutpal_38

19.2k views

nilutpal_38 commented Apr 2

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3 answers

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GATE CSE 2024 | Set 1 | Question: 45
The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time can be fully parallelized. The overhead for using an ... the parallelized code for an equal amount of time. The number of cores that minimize the execution time of the program is __________.

The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time ...

shivom

1.7k views

shivom commented Apr 2

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7

Data Representation and Arithmetic Algorithms
MULTIPLICATION OF (-15) AND (3) USING BOOTH'S ALGORITHM Please solve this question😭

MULTIPLICATION OF (-15) AND (3) USING BOOTH'S ALGORITHMPlease solve this question😭

Siddhi Jagtap

58 views

Siddhi Jagtap asked Apr 1

24 votes

3 answers

8

GATE CSE 2005 | Question: 67
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$

Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and ...

Nalinj

15.2k views

Nalinj commented Apr 1

4 votes

2 answers

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A computer has 64 bit instruction and 12 bit address.....how many 1-address instruction is possible?

A computer has 64 bit instruction and 12 bit address.If there are 250 3-address instruction and 525 2-address instruction,how many 1-address instruction is possible?

Rajsukh Mohanty

7.7k views

Rajsukh Mohanty commented Mar 23

1 votes

1 answer

10

Relative Addressing Mode
A two word instruction is stored in memory at an address designated by symbol W. The address field of the instruction (stored at W+1) is designated by symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by the Z. Which of the following is/are correct if the ... ] + (Y + 1) Z = (W + 2) + M [Y] Z = M[M[Y]] + Y Both (A) and (B)

A two word instruction is stored in memory at an address designated by symbol W. The address field of the instruction (stored at W+1) is designated by symbol Y. The opera...

ukone

10.8k views

ukone commented Mar 21

0 votes

1 answer

11

BARC 2024 CSE
How many 256 X 1K bit chips are required to build 1 MB of memory?

How many 256 X 1K bit chips are required to build 1 MB of memory?

mrtejas99

135 views

mrtejas99 answered Mar 18

2 votes

1 answer

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GATE CSE 2024 | Set 2 | Question: 47
A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a $16$-bit scalar field. If $8$ addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ___________.

A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two regi...

rexritz

1.7k views

rexritz commented Mar 18

2 votes

0 answers

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GATE CSE 2024 | Set 2 | Question: 48
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is then redesigned to operate on a $5$ ... hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ____________.

A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is the...

saurabhjoshi072002

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saurabhjoshi072002 commented Mar 15

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14

Made Easy Class Question.
Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below. S1 S2 S3 S4 I1 1 3 1 2 I2 1 1 3 1 I3 2 1 1 2 I4 1 1 1 2 (a) How many cycles are required to complete the ... ;= n; i++) { I1; I2; I3; I4; } The output of the instruction "I2" will be available after _____ cycles for I2.

Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below.S1S2S3S4I11312I21131I32112I41112...

Arjun

149 views

Arjun retagged Mar 6

1 votes

1 answer

15

GATE CSE 2024 | Set 2 | Question: 21
An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequence of instructions to be executed in a pipelined processor: $\text{I 1: DIV R3, R1, R2}$ ... $\text{I 3}$ There is a WAW dependency on $\text{R 3}$ between $\text{I 3}$ and $\text{I 4}$

An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequenc...

Counsellor

1.8k views

Counsellor edited Mar 6

1 votes

1 answer

16

GATE CSE 2024 | Set 2 | Question: 1
Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per ... $\text{DMA}$? $2,56,000$ $3,200$ $25,60,000$ $32,000$

Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle...

Counsellor

2.3k views

Counsellor edited Mar 6

1 votes

2 answers

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GATE CSE 2024 | Set 1 | Question: 46
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$ miss rate on instruction cache and $8 \%$ miss rate on data ... rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is __________.

A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$...

Counsellor

2.6k views

Counsellor edited Mar 6

1 votes

2 answers

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GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy. Both of them use the $\text{LRU}$ (Least Recently Used) block ... write miss in $\text{WTC}$ always writes the victim cache block to main memory before loading the missed block to the cache

Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy...

Counsellor

2.1k views

Counsellor edited Mar 6

2 votes

2 answers

19

GATE CSE 2024 | Set 1 | Question: 20
Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are ... cannot prevent all pipeline stalls Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Whic...

Counsellor

3.9k views

Counsellor edited Mar 6

11 votes

2 answers

20

GATE CSE 2023 | Question: 32
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip select $\text{(CS)}$ port of these memory blocks through a decoder as shown in the figure. The ... options is $\text{CORRECT}?$ $(0,1,2,3)$ $(0,1024,2048,3072)$ $(0,8,16,24)$ $(0,0,0,0)$

A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected t...

Srken

6.3k views

Srken commented Mar 6

52 votes

10 answers

21

GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below:$$\begin{array}{|...

sanjeet24

34.4k views

sanjeet24 answered Mar 4

1 votes

1 answer

22

Floating point number
what is the hexadecimal representation of the floating point number (-48.625) in single precision, after rounding off and normalisation

what is the hexadecimal representation of the floating point number (-48.625) in single precision, after rounding off and normalisation

randomAstrix007

1.8k views

randomAstrix007 commented Feb 28

9 votes

2 answers

23

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 53
Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$ $\textsf{0x80000004}$ $\textsf{0x80000008}$ $\textsf{0x80000010}$ $\textsf{0x80000002}$

Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$$...

Silver_Reaper

809 views

Silver_Reaper commented Feb 26

1 votes

1 answer

24

GATE CSE 2024 | Set 2 | Question: 51
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$ ... the number of bits used to encode the immediate value/address field. The value of $\text{X+2Y+Z}$ is __________.

A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instruc...

Suraj7

1.7k views

Suraj7 answer edited Feb 23

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0 answers

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Gate 2024 CS/IT shift-2 Question 61
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below. ... the number of bits used to encode the immediate value/address field. The value of 𝑋 + 2𝑌 + 𝑍 is ________

A processor uses a 32-bit instruction format and supports byte-addressable memoryaccess. The ISA of the processor has 150 distinct instructions. The instructions areequal...

Hira Thakur

202 views

Hira Thakur closed Feb 19

0 votes

2 answers

26

GATE CSE 2024 | Set 1 | Question: 5
Which one of the following statements is FALSE? In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle For bulk data transfer, the burst mode of ... driven I/O mechanism The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Which one of the following statements is FALSE?In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a s...

makhdoom ghaya

2.1k views

makhdoom ghaya edited Feb 18

0 votes

0 answers

27

#Self doubt COA

Çșȇ ʛấẗẻ

320 views

Çșȇ ʛấẗẻ asked Feb 16

81 votes

4 answers

28

GATE CSE 2015 Set 2 | Question: 44
Consider the sequence of machine instruction given below: ... forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.

Consider the sequence of machine instruction given below:$$\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7,...

xd_punk

26.4k views

xd_punk commented Feb 10

1 votes

1 answer

29

GATE Overflow Test Series | Mock GATE | Test 6 | Question: 39
A Hard disk is connected to a $2$ GHz processor through a DMA controller. Assume that the initial setup time for a DMA transfer takes $800$ clock cycles for the processor and also assume that the handling of the ... time consumed by the disk, assuming that the data are transferred only during the idle cycles of the CPU is _______

A Hard disk is connected to a $2$ GHz processor through a DMA controller. Assume that the initial setup time for a DMA transfer takes $800$ clock cycles for the processor...

rishabh-441

286 views

rishabh-441 commented Feb 8

11 votes

2 answers

30

GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check for a keystroke and consumes $100\; \mu \mathrm{s}$ (micro seconds) for ... interrupt and processing a keystroke. The ratio $\dfrac{T_{1}}{T_{2}}$ is _____________. (Rounded off to one decimal place)

A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check ...

Bhaskar_Saini

8.0k views

Bhaskar_Saini answer edited Feb 8

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