IITD MS CSE Interview Experience.
There was a programming test before the interview – 5 questions, Codechef style. Here are the questions:
Out of 300 odd people who appeared for the test, 80 were shortlisted for the interviews. I managed to solve two problems completely (200/500), and my rank was 31 out of the 300 odd people and hence was called for the interview.
The meeting was on Microsoft Teams, they had said they might call anytime between 3 pm to 5:30 pm. My turn came around 4:15 pm.
There were 8 professors, out of which 4 asked me questions. They were:
Prof Smriti Sarangi (CompArch), Prof Sorav Bansal (Compilers, OS), Prof Priti Ranjan Panda (Embedded Systems) and Prof Subodh Kumar (HPC, Parallel Programming).
They read out my bio, my interests (Computer Architecture, Operating Systems) and started asking one by one.
SS: So you're interested in COA, what all topics are comfortable in?
Ans: Sir, caches, pipelining, performance metrics etc.
SS: How do you define performance? How is it related with frequency?
Ans: Performance is inversely proportional to execution time, but in overall performance frequency is one component - we need to know insts, CPI and frequency - which I elaborated with the standard equation.
Then he asked me a bunch of questions related to pipelining (how do stalls affect CPI, how do you mitigate them,etc etc), which I don't remember as they were mostly extensions of one question after another.
SS: Okay, if I want to increase performance, what's stopping me from using a 1000 GHz processor?
Ans: Sir, if you increase the frequency, the amount of time will decrease so in a small unit of time, I guess much work can't be done. It'll also lead to increase in power, for which you'll need an efficient cooling system.
SS: Okay, your answer is 75 % right. What else could be the reason?
Ans: [Thought for a while] Sir, latching would be a problem too. In too small a clock cycle, you won't be able to latch to take it from one stage to another.
[He was satisfied now.]
SS: Okay, suppose you have a computer which only has a processor and RAM, can you still make it work without a disk, from some other computer's memory?
Ans: I said yes sir, I've read about how you can remotely boot an OS so in a similar way, maybe we can use a protocol which might allow you to access the data from a remote location.
SS: Yes, you are correct. Such a protocol exists and it's called RDMA.
SS: Okay, I'll ask you one last trick question, just say yes or no, don't elaborate - suppose you have infinite physical memory, do you still need virtual memory? Ans: Yes sir, because we still need isolation which is an important component of modern day OSes.
SS: Okay, elaborate that [wtf? you said don’t elaborate] Ans: Then I explained him VAS, PAS and all that stuff.
Next, Prof Sorav started asking questions. He asked a bunch of questions about how the page table, cache and memory interact with each other, which I was able to answer well. Then he asked some convoluted question, which I think I was unable to understand properly as I gave him some other answer, then he realised okay I think we’re not able to get through the question properly.
SB: Have you heard about huge pages? What are they?
Ans: Yes sir, huge pages are used when you need pages which are much larger than 4 KB or the default size. Linux uses something called as THP (Transparent Huge Pages).
SB: Okay, can you elaborate what is that?
Ans: Sir, the TLB stores VA-PA mappings and since it’s a cache, it has to be small. But at the same time, we want to increase our TLB reach, so that we have lesser thrashing of the TLB itself.
As I was further explaining, he stopped me and said Okay, I’ve got the answer that I need.
Then Prof Priti Panda.
PP: You mentioned critical path somewhere when we were talking about caches, can you elaborate what is that?
Ans: it’s the path which takes the longest time to execute in a circuit etc etc.
PP: Okay, so suppose we need to formulate this is a problem and design an algorithm to find the critical path, how would you do that?
Ans: I was a bit stumped, and suggested some methods, then I asked if he wants a particular data structure to which he said yes, then I said maybe we can use graphs sir where the nodes are the gates and the weights of the edges are the timing delays of that particular gate.
PP: So do you mean all the outgoing edges of a gate will have the same delay?
Ans: Not sure, but I guess yes sir.
He didn’t seem much satisfied, but whatever, he said I am done and we moved on to professor Subodh. He only asked me one question - given a BST and [a.b], how will you print all the numbers between it? (yes, the same GATE 2020 question.) We had a 10 minute discussion on it as I knew the overall approach, but not the fine details of it.
And that was it.
Overall, it was an okay interview - I guess average. Some questions were hit, some were miss.
They did ask me which subjects I was interested in (could be also because I had talked to Smriti sir before the interviews and he had told me he’ll ask me CompArch)