IITM MS Interview:
Primary Subject: Computer Architecture
Panel 1, Profs were John Augustine, Balaraman Ravindran, Chandra Shekar(the HoD of the department)
I was asked programming by Prof John, COA by Prof Chandra.
[They asked me if I had any MTech offer, I said only as a backup.]
Programming was simple (although I did screw up).
Given a binary 2D matrix, return true if each row and each column has at least five 1s, or return false.
[They wanted you to write proper functional C code, down to the braces as well.]
This went on for 10ish minutes, I made a major logical error. [Prof Balaraman explicitly said you're not missing a corner case, you're missing a major case]
Either way, I couldn't arrive at the correct answer. I said I know this is incorrect, but I need a bit of time to debug, to which they said that in the interest of time, we'll move on to other subjects.
Then Prof Chandra asked COA questions:
1. What is the usual cache hierarchy?
A: Told him about L1, L2, L3 and other basic stuff.
2. What are their usual access times? Why is L2 cache slower than L1 cache?
A: Told him that a larger and faster cache at the same time isn't possible, there'll be propagation delays etc. (which is a valid answer btw).
He didn't seem convinced by that answer, wanted something else.
This was followed by a discussion on the internals of the cache - sets, multiplexors and stuff like that. Anything I said, he had a valid (sometimes invalid?) counterpoint to it.
3. What is an inclusive cache?
A: Told him the definition. Awkward silence after that, I don't know what else he expected.
A small discussion followed - on what happens when a block from L1 is evicted, L2 is evicted, things like that.
4. If you do a context switch, is the cache content flushed?
A: No sir, because data can be shared among processes.
5. Is L1 cache split? Why do you need split, and not unified?
A: Told him that i-cache has to be close to the processor, D-cache close to the memory, so that's a major reason why they are split.
Again, he didn't seemed convinced. Wanted some other answer. He hinted that it's related to pipelining and how different instructions can access different caches at the same time.
A: Yes sir, because one instruction can be in IF, one in MEM so you a split cache would work better. That's also a reason why we need a split L1 cache.
He said that's the only reason we need a split L1 cache, and started laughing.
6. Okay, what about L2 cache and onwards?
A: Split sir, but don't exactly know the reason. Maybe bigger unit, so parallel access is possible.
He laughed again, and said okay, we're done with the interview.
Overall, programming was bad (from my side) and COA was okay.
I guess there is some component of GATE score as well because the same panel asked another student with same subject very basic questions in COA, nothing in depth. Their entire interview lasted 10-12 minutes. Mine lasted 30 minutes. I've no idea why this discrepancy in the same panel.