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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

       Topic Covered in Videos Video link from GO Youtube channel
  • Programs and Data
  • Data Representation
  • Registers and Memory
  • Instructions, Addressing Modes
  • A RISC Instruction Set
  • Function Call and Return
  • Instruction Execution
  • Software organization
  • Pipelining
  • Pipeline hazards
  • Cache memory
  • Memory hierarchy
  • Cache operation
  • Cache aware programming
  • Data Dependencies in Pipeline
GO Videos

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posted Oct 7 in Study Materials by Veteran (52,769 points)
edited Oct 7 by | 149 views
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