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Recent posts tagged gate-cse

10
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register read ... clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
posted Mar 9, 2017 in Others Dhawal Gajwe 1,457 views
11
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
posted Feb 12, 2017 in Useful Links Anup patel 3,945 views
12
Choose the correct alternatives ( more than one may be correct) and write the corresponding letters only: (viii) A non-planar graph with minimum number of vertices has (a) 9 edges, 6 vertices (b) 6 edges, 4 vertices (c) 10 edges, 5 vertices (d) 9 edges, 5 vertices
posted Dec 28, 2016 in Programming & Data Structures Arjun 2,922 views
13
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: A $2-3$ tree is such that All internal nodes have either $2$ or $3$ children All paths from root to the leaves have the same length. The number of internal nodes of a $2-3$ tree having $9$ leaves could be $4$ $5$ $6$ $7$
posted Dec 28, 2016 in Digital Logic Arjun 4,289 views
14
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Which of the following problems is not $NP$-hard? Hamiltonian circuit problem The $0/1$ Knapsack problem Finding bi-connected components of a graph The graph coloring problem
posted Dec 28, 2016 in Compiler Design Arjun 3,436 views
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