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Recent posts tagged gate2017

Consider a relation scheme $R = (A, B, C, D, E, H)$ on which the following functional dependencies hold: {$A \rightarrow B$, $BC \rightarrow D$, $E \rightarrow C$, $D \rightarrow A$}. What are the candidate keys R? $AE, BE$ $AE, BE, DE$ $AEH, BEH, BCH$ $AEH, BEH, DEH$
posted Mar 13, 2017 in Others AmitPatil 2,484 views
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register read ... clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
posted Mar 9, 2017 in Others Dhawal Gajwe 1,438 views
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
posted Feb 12, 2017 in Useful Links Anup patel 3,868 views
Consider the following $2-3-4$ tree (i.e., B-tree with a minimum degree of two) in which each data item is a letter. The usual alphabetical ordering of letters is used in constructing the tree. What is the result of inserting $G$ in the above tree? None of the above
posted Feb 11, 2017 in Others Wali 320 views
The following is a scheme for floating point number representation using 16 bits. Bit Position 15 14 .... 9 8 ...... 0 s e m Sign Exponent Mantissa Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the ... maximum difference between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$
posted Feb 10, 2017 in Motivation Arjun 861 views
A computer uses $32-bit$ virtual address, and $32-bit$ physical address. The physical memory is byte addressable, and the page size is $4$ $\text{kbytes}$ . It is decided to use two level page tables to translate from virtual address to physical ... entries that can be contained in each page? How many bits are available for storing protection and other information in each page table entry?
posted Feb 4, 2017 in Others Habibkhan 2,932 views
Consider the following algorithm for searching for a given number $x$ in an unsorted array $A[1..n]$ having $n$ distinct values: Choose an $i$ at random from $1..n$ If $A[i] = x$, then Stop else Goto 1; Assuming that $x$ is present in $A$, what is the expected number of comparisons made by the algorithm before it terminates? $n$ $n-1$ $2n$ $\frac{n}{2}$
posted Feb 3, 2017 in Others smartmeet 1,604 views
A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $(T1)$, which occupies exactly one page. Each entry of $T1$ stores the base address of a page of ... cache block size is $64$ bytes. What is the size of a page in $KB$ in this computer? $2$ $4$ $8$ $16$
posted Nov 17, 2016 in Preparation Advice Arjun 2,551 views
Yess ~L is also not empty :). But would you like to shed some light on the the way you transform the RE's complement into L or ~L. The way I think both of them are NonRE is combination of some RE language and some NonRE language will always be NonRE unless their union is Universal!..isn't it correct?. this question seems to be way too much tricky!
posted Nov 12, 2016 in Preparation Advice Arjun 2,258 views
I am still of the opinion that we cannot take only one inverter, since inverter is an input to the two different the AND gates A'C' and A'B'. Though, it is the same inverter that is used, but it is used twice with different combination of another input to ... . You are just calculating the number of inverters and number of gates(AND/OR) but not checking from where the input is coming/going to.
posted Nov 6, 2016 in Preparation Advice Arjun 9,850 views
(a) is true. Ada supports in-out parameter passing, which is nothing other than call by value result (but Ada in GATE syllabus?) (b) Not true. (c) Most robust? I don't know what is meant by robust here. (d) Not true. (e) Not ... every occurrence of the formal paramater and hence efficiency will only be less. Reference:
posted Aug 15, 2016 in Announcements Arjun 183 views
Register renaming is done in pipelined processors: as an alternative to register allocation at compile time for efficient access to function parameters and local variables to handle certain kinds of hazards as part of address translation
posted Mar 19, 2016 in Study Materials Arjun 1,695 views
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