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Recent posts tagged gate2017

4
When the revised answer keys for GATE will be released?
Hello, I just wanted to know that when IIT R will release revised answer key after accepting challenges from students? Will there be any changes in CS GATE 2017 answer key(Set 1 and Set 2)? After how many days IISc(GATE 2016 organiser) had uploaded revised answer key for GATE 2016? Was there any change?
Consider a relation scheme $R = (A, B, C, D, E, H)$ on which the following functional dependencies hold: {$A \rightarrow B$, $BC \rightarrow D$, $E \rightarrow C$, $D \rightarrow A$}. What are the candidate keys R? $AE, BE$ $AE, BE, DE$ $AEH, BEH, BCH$ $AEH, BEH, DEH$
posted Mar 13, 2017 in Others AmitPatil 2,484 views
5
Bharat Sanchar Nigam Limited: Unfair to freshers (Engineering candidates)
Sign the petition please.... https://www.change.org/p/bharat-sanchar-nigam-limited-unfair-to-freshers-engineering-candidates?recruiter=false&utm_source=share_petition&utm_medium=copylink Respected Sir/Ma'am, With ... degree in 2017. Hoping that you would understand our concerns regarding this. Final year students
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register read ... clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
posted Mar 9, 2017 in Others Dhawal Gajwe 1,438 views
8
GATE 2017 CSE Morning+Afternoon Session OFFICIAL Question + Answer Key
You can find Some questions and their solution here [UPDATED] Morning Session : http://gatepoint.org/gate-2017-cse-morning-shift-question-paper-solution/ Afternoon Session : http://gatepoint.org/gate-2017-cse-afternoon-session-answer-key/
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
posted Feb 12, 2017 in Useful Links Anup patel 3,868 views
9
Some confusion about instruction
Hello,I have small confusion.When answer is submitted at the end of exam,there was a column 'Marked for review'. I answered about 10 question and marked it for review.Eventually exam ended.Will the 'answered and marked for review' question will be counted? Just confused as there was a separate column for the same.
Consider the following $2-3-4$ tree (i.e., B-tree with a minimum degree of two) in which each data item is a letter. The usual alphabetical ordering of letters is used in constructing the tree. What is the result of inserting $G$ in the above tree? None of the above
posted Feb 11, 2017 in Others Wali 320 views
10
Tensed?
I guess many of you will be tensed. But you should not be. GATE exam won't need tension or memory or anything other than presence of mind. It just checks what all you know. All you need to do is to answer the ones you know, ensure no silly mistakes, read and understand ... clear. So, the thing is take GATE as a step- not as an end. It is never the end for good or bad. Best of Luck
The following is a scheme for floating point number representation using 16 bits. Bit Position 15 14 .... 9 8 ...... 0 s e m Sign Exponent Mantissa Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the ... maximum difference between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$
posted Feb 10, 2017 in Motivation Arjun 861 views
11
BEST WISHES FOR GATE 2017
Hello friends !! Good morning !! First of all I would like to owe my gratitude to Gateoverflow for the knowledge and experience also to some extent that I have been gaining from it..Really many concepts are cleared and also in the solving process of ... possible..And remember the quote : Even the word "impossible" says " I m possible ".. Thank you all.
A computer uses $32-bit$ virtual address, and $32-bit$ physical address. The physical memory is byte addressable, and the page size is $4$ $\text{kbytes}$ . It is decided to use two level page tables to translate from virtual address to physical ... entries that can be contained in each page? How many bits are available for storing protection and other information in each page table entry?
posted Feb 4, 2017 in Others Habibkhan 2,932 views
12
A great journey of GATE2017 is about to reach at it's milestone!
I'm a guy from fiinal year Computer Engineering from a private college. When I joined Engineering I'm very curious about everything about Computing! I entered in college with dreams of innovating something different in this tech-world ... P.S. I know this is very long, but I am just overhelmed with my emmotions right now!
Consider the following algorithm for searching for a given number $x$ in an unsorted array $A[1..n]$ having $n$ distinct values: Choose an $i$ at random from $1..n$ If $A[i] = x$, then Stop else Goto 1; Assuming that $x$ is present in $A$, what is the expected number of comparisons made by the algorithm before it terminates? $n$ $n-1$ $2n$ $\frac{n}{2}$
posted Feb 3, 2017 in Others smartmeet 1,604 views
15
Preparing to be in IISc/top IITs - 3rd Blog
Are you preparing well? Except a very few most would not say "yes" to this. Some people are very confident with their concepts and most others are in tension. So what to do? My advise - Take a day break. Do whatever that makes you ... I just wanted to say these for a long time. Hope I have said everything now. All the best for GATE 2017 :)
A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $(T1)$, which occupies exactly one page. Each entry of $T1$ stores the base address of a page of ... cache block size is $64$ bytes. What is the size of a page in $KB$ in this computer? $2$ $4$ $8$ $16$
posted Nov 17, 2016 in Preparation Advice Arjun 2,551 views
16
Preparing to be in IISc/top IITs - 2nd Blog
I have been getting many emails/messages about preparation advice. So, thought of adding some more points. Previous blog was more about what not to do for preparation. Here I'm going to reply to many of the FAQs I'm getting. I have ... have told to keep test series to minimum level - but not to stop solving problem ON OWN. This is very very important.
Yess ~L is also not empty :). But would you like to shed some light on the the way you transform the RE's complement into L or ~L. The way I think both of them are NonRE is combination of some RE language and some NonRE language will always be NonRE unless their union is Universal!..isn't it correct?. this question seems to be way too much tricky!
posted Nov 12, 2016 in Preparation Advice Arjun 2,258 views
17
Preparing to be in IISc/top IITs
Hi, There are many people here preparing to be in Top 100 or even better. Of course if you are preparing for GATE you should not think below that. GATE is not a difficult exam to get to top 100. So, let me tell somethings I have seen over ... MS/Ph.D. But this does not mean one with rank say 400 can get it. Research interviews are different from an objective exam.
I am still of the opinion that we cannot take only one inverter, since inverter is an input to the two different the AND gates A'C' and A'B'. Though, it is the same inverter that is used, but it is used twice with different combination of another input to ... . You are just calculating the number of inverters and number of gates(AND/OR) but not checking from where the input is coming/going to.
posted Nov 6, 2016 in Preparation Advice Arjun 9,850 views
18
Feedback for the Exams
Those who have taken the online exam here, please give the feedback. GATE Overflow test was supposed to start last weekend, but got delayed by a few days. It will start in 2 days. Now, you can view the exam results any time. A leaderboard and ranking will be added soon :)
(a) is true. Ada supports in-out parameter passing, which is nothing other than call by value result (but Ada in GATE syllabus?) (b) Not true. (c) Most robust? I don't know what is meant by robust here. (d) Not true. (e) Not ... every occurrence of the formal paramater and hence efficiency will only be less. Reference: http://courses.cs.washington.edu/courses/cse341/03wi/imperative/parameters.html
posted Aug 15, 2016 in Announcements Arjun 183 views
19
News Updates for GATE 2017
Please follow this blog (favorite button to the right end of post title) for getting news updates related to GATE 2017 preparation.
Register renaming is done in pipelined processors: as an alternative to register allocation at compile time for efficient access to function parameters and local variables to handle certain kinds of hazards as part of address translation
posted Mar 19, 2016 in Study Materials Arjun 1,695 views
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