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Recent posts in CO & Architecture

Basics required: 1-Basic operation of computer 2-Memory addressing and languages 3-software and architecture types( watch from 14:26 seconds ) 4-Instruction Set architecture 5-Representation of numbers 6-measuring of CPU performance(importantfor pipelining) Actual syllabus: 7-Inst ... this subject is highly recommended. I will edit this blog if i find any good sources in future. Thank you :)
posted Mar 2, 2020 in CO & Architecture chirudeepnamini
edited Mar 7, 2020 by chirudeepnamini
Most people have trouble with Cache Misses. You can go through this:
posted Jan 28, 2019 in CO & Architecture Arjun 1,028 views
Introduction Slides Data Dependence and Data/Control Hazards Video Reference Slides Adding the corrected pipeline diagram for the question discussed in the video:
posted Jan 27, 2019 in CO & Architecture Arjun
edited Jan 28, 2019 by Arjun
A CPU uses two levels of caches L1 and L2. It executes two types of jobs J1 and J2. Their details are as follows: (A) J1 comes with a probability of 0:3 and requires 2000 memory references, all for reading. For J1, there are 100 misses in L1 and 60 ... What is the average memory access time? Please Sir help me with this .. I am really getting confused about how to approach for this question .
posted May 2, 2016 in CO & Architecture Payel 536 views
Important Ones Difficult Ones Question regarding Minimum Average Latency from Dynamic Pipeline portion asked once in 2015. Extra Questions Caches More Problems on Cache Solution Quiz 1 Quiz 2
posted Aug 4, 2015 in CO & Architecture Arjun
edited Feb 2 by Arjun
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