Recent posts in CO & Architecture


Basics required:

1-Basic operation of computer

2-Memory addressing and languages

3-software and architecture types( watch from 14:26 seconds )

4-Instruction Set architecture

5-Representation of numbers

6-measuring of CPU performance(importantfor pipelining)


                                                                 Actual syllabus:

7-Inst format and addressing modes

Control unit:

8-Introduction to Control unit

9-Explaining control steps for instructions..

10-Some more examples

11-Implementation and types of control unit


12-How processor and memory interact

13-Memory interfacing and addressing

14-Memory hierarchy and some important definitions

15-Some numericals on Memory hierarchy 

16-Mapping techniques in cache

17-Types of cache misses,cache write stratergies,

18-Improving performance of cache


19-Basic concepts of pipeling

20-Pipeline scheduling

21-Intro to data hazards

22-hazards while accessing memory and types of hazards

23-Control hazards( watch till 15:11 seconds)

Input output

24-Secondary storage devices( watch till 24:33 seconds. you can watch till the end if you want)

25-IO organization

26-Data transfer techniques

27-Interrupt handling-1

28-Interrupt handling-2

29-Direct memory access

If you are not satisfied or couldn’t understood any topic in above videos,you can refer those in below courses.

Some other sources:





Computer Organization by Prof. S. Raman

Computer Organization by Prof.P.K. Biswas

High performance computing by prof.Matthew jacob

Answer by bikram sir

Nptel web course

carry and overflow


Do these only after you’re done with previous gate questions.



course3(Highly recommended to solve these assignments)


for some topics like arithmetic you can refer Carl hamacher ,Marris mano.

Note:The above sources are not exhaustive.

I may have missed some topics.But you can cover them through textbooks and while solving questions.

All the videos are taken from this course.Incase i have missed or misplaced any video links,you can refer the nptel course.

Completing Digital logic subject before starting this subject is highly recommended.

I will edit this blog if i find any good sources in future.

Thank you :)


chirudeepnamini posted in CO & Architecture Mar 2, 2020 edited Mar 7, 2020 by chirudeepnamini

Most people have trouble with Cache Misses. You can go through this:

Arjun posted in CO & Architecture Jan 28, 2019
by Arjun

Adding the corrected pipeline diagram for the question discussed in the video:

Arjun posted in CO & Architecture Jan 27, 2019 edited Jan 28, 2019 by Arjun
by Arjun
A CPU uses two levels of caches L1 and L2. It executes two types of
jobs J1 and J2. Their details are as follows:
(A) J1 comes with a probability of 0:3 and requires 2000 memory references,
all for reading. For J1, there are 100 misses in L1 and 60
misses in L2.
(B) J2 comes with a probability of 0:7 and requires 3000 memory references,
all for reading. For J2, there are 50 misses in L1 and 70
misses in L2
The L1 hit time is 2 cycles and the L2 hit time is 10 cycles. The L2 miss
penalty is 200 cycles. What is the average memory access time?


Please Sir help me with this .. I am really getting confused about how to approach for this question .
Payel posted in CO & Architecture May 2, 2016
by Payel
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