Recent questions and answers in CO & Architecture

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1

Effective address
Choose the correct formula for Effective Address calculation Base + (Size*Scale) +Displacement) (Base + Size)*Scale +Displacement Base + Size*(Scale +Displacement) (Base + Size)*(Scale +Displacement)

answered 7 hours ago in CO & Architecture by Dharmendra Verma Junior (687 points) | 6 views

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1 answer

2

Test_CO1_Q34
Consider a device that is to transfer data at a rate of 1 Mbytes/sec in 16bytes chunks. The overhead of polling is 400 cycles on 500 Mhz processor. Calculate the overhead of polling assuming I/O uses polling mechanism to transfer data? A. 5% B. 8% C. 6% D.4%

answered 7 hours ago in CO & Architecture by Dharmendra Verma Junior (687 points) | 9 views

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1 answer

3

Number of bits - Instruction format
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 ... and an address part. How many bits are there in the operation code, the register code part, and the address part respectively?

answered 8 hours ago in CO & Architecture by Dharmendra Verma Junior (687 points) | 11 views

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4

DOUBT: isn't this is a pipelining question

asked 10 hours ago in CO & Architecture by Ashwani Yadav (173 points) | 9 views

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5

self doubt
suppose we have 50 control signal and suppose 49 control signals are active, Q1:consider horizontal micro programed control unit what is the length of control word in bits? Q2: consider vertical micro programed control unit what is the length of control word in bits?

asked 2 days ago in CO & Architecture by eyeamgj Active (5.1k points) | 22 views

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0 answers

6

WHAT IS CORRECT ANSWER?
https://gateoverflow.in/1269/gate2007-71 ANSWER SHOULD BE 11?? OR 21?

asked 2 days ago in CO & Architecture by eyeamgj Active (5.1k points) | 8 views

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0 answers

7

Process state
A printf or malloc takes the process to what state? Running Ready Suspended Terminated

asked 2 days ago in CO & Architecture by Balaji Jegan Active (2.2k points) | 8 views

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2 answers

8

cache memory
Number of sets = 128 2 way set Associative Cache size = 4Kbytes Main memory has 21 bit address What are the sizes of the cache blocks and number of cache blocks respectively?

answered 3 days ago in CO & Architecture by garimanand Junior (677 points) | 21 views

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9

Test_CO1_Q35
Assume branch instruction occurs 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% if the time with useful instructions, 20% of the ... What is the new CPI due to load delay slots and branch hazards? A. 1.204 B. 1.404 C. 2.204 D. 4.404

asked 3 days ago in CO & Architecture by BOB (131 points) | 8 views

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10

self doubt
what is the principle of inclusion in cache . pleasse explain in simple terms

asked 3 days ago in CO & Architecture by Deepanshu Active (3.2k points) | 8 views

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0 answers

11

CPU ORGANIZATION
a system has 13 bit instruction and supports one address and zero address instruction.if there are 32 one address instructions,how many zero address instructions are supported by the processor (assume 128-word memory) 1)2048 2)1024 3)3072 4)4096

asked 3 days ago in CO & Architecture by altamash (91 points) | 19 views

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12

*** TEST SEries

asked 3 days ago in CO & Architecture by Chetan28kumar (47 points) | 18 views

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13

test series co
r1 ← r2 − r3 M[r1 + 100] ← r2 how many RBW AND WBW DEPENDENCY???

asked 3 days ago in CO & Architecture by eyeamgj Active (5.1k points) | 10 views

0 votes

1 answer

14

COA:- Average stalls per instruction
What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer

answered 4 days ago in CO & Architecture by Masterk (11 points) | 161 views

+17 votes

6 answers

15

GATE2006-80
A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. Consider the following two C code segments, $P1$ and $P2$. P1: for (i=0; i<512; i++) { ... cache misses experienced by $P1$ be $M_{1}$and that for $P2$ be $M_{2}$. The value of $M_{1}$ is: $0$ $2048$ $16384$ $262144$

answered 5 days ago in CO & Architecture by Mostafize Mondal Junior (553 points) | 3.3k views

+1 vote

1 answer

16

Q34- The above circuit represents __________ stages.

answered 5 days ago in CO & Architecture by Khalid Ansari (11 points) | 184 views

+33 votes

2 answers

17

GATE2008-71
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bi$t virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows ... those to array $ARR$. The total size of the tags in the cache directory is: $32$ $Kbits$ $34$ $Kbits$ $64$ $Kbits$ $68$ $Kbits$

answered 5 days ago in CO & Architecture by Vaibhav Raj Singh (151 points) | 4.5k views

+1 vote

1 answer

18

****** Test Series
A memory system consisting of two levels L1 and L2 . The required access times of those are 10 ns and 120 ns respectively. Another memory system has also two levels L3 and L4 whose access times are 15 ns and 150 ns respectively. The hit ratio of ... twice than that of first system. If the two memory systems follow simultaneous memory access, what is the hit ratio of first system?

answered 5 days ago in CO & Architecture by Prince Sindhiya Active (3.6k points) | 81 views

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0 answers

19

Operand Forwarding
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage takes one cycle. How many instructions must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6

asked 5 days ago in CO & Architecture by Na462 Loyal (6.4k points) | 26 views

+1 vote

1 answer

20

Efficiency of Stop-and-Wait, Selective Reject and Go-Back-N ARQ when error probability is p

answered 5 days ago in CO & Architecture by akharatgate (39 points) | 416 views

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0 answers

21

COROUTINES AND POSITION INDEPENDENT CODE

asked 6 days ago in CO & Architecture by eyeamgj Active (5.1k points) | 9 views

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0 answers

22

Microprogramming
A micro program control unit is required to generate a total of 25 control signals. Assume that during any micro instruction, at most two control signals are active. The number of bits required in the control word to generate the required ... this question I am asking about horizontal microprogramming) previous year gate question link:https://gateoverflow.in/2754/gate1996-2-25

asked 6 days ago in CO & Architecture by Vishnathan (189 points) | 19 views

0 votes

1 answer

23

Clock per instruction
What is the difference between Effective CPI and Average CPI ? A program is run on 40 MHZ with instruction mix and corresponding clock cycle count. Determine : * Effective CPI * Average CPI Instruction Clock Cycle Instruction Count Arithmetic 1 45000 Floating Point 2 32000 Data Transfer 2 15000 Control Transfer 2 8000

answered 6 days ago in CO & Architecture by Dharmendra Verma Junior (687 points) | 15 views

0 votes

0 answers

24

No of cache misses

asked 6 days ago in CO & Architecture by Shubhanshu Boss (15.6k points) | 43 views

0 votes

1 answer

25

Addressing Mode
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000

answered 6 days ago in CO & Architecture by SHUBHAM SHASTRI Boss (10.1k points) | 30 views

0 votes

0 answers

26

SELF DOUBT REGISTER REFERENCE
MOV R1 #23 HOW MANY REGISTER REFERENCES ARE REQUIRED?

asked 6 days ago in CO & Architecture by eyeamgj Active (5.1k points) | 8 views

+54 votes

8 answers

27

GATE2004-47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and ... 000$ instructions. What is the effective average instruction execution time? $645$ $nanoseconds$ $1050$ $nanoseconds$ $1215$ $nanoseconds$ $1230$ $nanoseconds$

answered Oct 12 in CO & Architecture by Ashish Patel (235 points) | 13.2k views

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1 answer

28

Branch Offset
Consider a processor where each instruction size is exactly two bytes long. Conditional and unconditional branch instructions use PC relative addressing mode with offset specified in Bytes to the target location of the branch instruction; the offset is always with ... sequence. The below program is executed (All values are specified in decimal), type of memory is byte addressable

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 23 views

0 votes

1 answer

29

TESTBOOK TEST SERIES

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 56 views

+2 votes

2 answers

30

Cache Mapping

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 42 views

0 votes

1 answer

31

ACE TEST SERIES QUESTION

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 38 views

0 votes

1 answer

32

Number of 1 address instructions
How many maximum number of one address instructions possible?

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 25 views

0 votes

2 answers

33

Number of 0 address instructions possible

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 24 views

0 votes

2 answers

34

Number of 1 address instructions
How many maximum number of 1 address instructions supported?

answered Oct 11 in CO & Architecture by Dharmendra Verma Junior (687 points) | 25 views

0 votes

1 answer

35

Pipeline
@Arjun sir In the Question :- https://gateoverflow.in/1391/gate2005-68 I have drawn like :- F D E M W F D D E M W F - D E M W Total 8 Clock cycle with operand forwarding. Why cant we Overlap stuffs means:- In first case at second instruction ... cycles. Checkout the comment of Arjun Sir:- https://gateoverflow.in/3623/gate2006-it-79 Or when to use such technique as depicted by Arjun Sir.

answered Oct 11 in CO & Architecture by Things To Know (Thin Junior (553 points) | 62 views

0 votes

1 answer

36

Number of 0 address instructions
How many maximum number of zero address instructions possible?

answered Oct 11 in CO & Architecture by Navneet Kalra Junior (589 points) | 17 views

0 votes

0 answers

37

Number of 2 address instructions
How many maximum number of 2 address instructions possible?

asked Oct 10 in CO & Architecture by Balaji Jegan Active (2.2k points) | 11 views

0 votes

1 answer

38

GRADE UP TEST SERIES
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. The clock cycle of the CPU is 10 microseconds and word length of CPU is 32 bits. What percentage of time is the CPU in busy mode (upto 2 decimal place) ?

answered Oct 10 in CO & Architecture by Dharmendra Verma Junior (687 points) | 9 views

0 votes

1 answer

39

PipeLine

answered Oct 10 in CO & Architecture by Things To Know (Thin Junior (553 points) | 559 views

+1 vote

1 answer

40

Minimum clock cycle

answered Oct 10 in CO & Architecture by Things To Know (Thin Junior (553 points) | 55 views

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