Recent questions and answers in CO & Architecture

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1

Gate Theory
when any theory question is asked how to attempt them in Gate. Is it required to read the standard text books for these things to answer?

asked 1 hour ago in CO & Architecture by Nihar Ranjan Panda (33 points) | 4 views

+1 vote

1 answer

2

Computer Architecture
In signed-magnitude binary division, if the dividend is (11100) and divisor is (10011) then the result is A. (00100) B. (10100) C. (11001) D. (01100) Please Explain

answered 3 hours ago in CO & Architecture by Nayan Bhatia (11 points) | 163 views

0 votes

1 answer

3

addressing modes in coa.
A computer supports one address and two address instructions. All the Addresses are the memory addresses. Memory size is 1Mbyte. How many one address instructions are possible if it has 240 two addresses instructions? (Assume binary instructions code has 48 bits)

answered 4 hours ago in CO & Architecture by Hradesh patel Loyal (7.1k points) | 15 views

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0 answers

4

Memory Hierarchy
if simply the access time of level-1 meomry and level-2 memory is given and hit ratio is given then for average time access what should be the approach? should i go for hierarchical or simultaneous access?

asked 11 hours ago in CO & Architecture by Nihar Ranjan Panda (33 points) | 19 views

+1 vote

0 answers

5

Patterson-Henessey, Pipelining
Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been written into the register file and so, there should be three stalls? From what I could understand in this question, the value of the registers is available after the M stage, before it is written.

asked 1 day ago in CO & Architecture by goxul Active (1.1k points) | 6 views

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0 answers

6

Self doubt
In case of CISC, why more number of addressing modes helps in faster exectuion of program?

asked 1 day ago in CO & Architecture by Anuranjan Chauhan (277 points) | 17 views

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0 answers

7

self doubt(NPTEL assignment)
Encode the instruction sub r1, r2, 3 (a) 00001 0 0001 0010 00 0000 0000 0000 0011 (b)00001 1 0001 0010 00 0000 0000 0000 0011 (c) 00011 1 0001 0010 00 0000 0000 0000 0111 (d)None of the above

asked 2 days ago in CO & Architecture by BASANT KUMAR Junior (799 points) | 18 views

+18 votes

5 answers

8

GATE1992-5-a
The access times of the main memory and the Cache memory, in a computer system, are $500$ $n sec$ and $50$ $nsec$, respectively. It is estimated that $80$% of the main memory request are for read the rest for write. The hit ratio for the read ... write-through policy (where both main and cache memories are updated simultaneously) is used. Determine the average time of the main memory.

answered 2 days ago in CO & Architecture by Prateek Raghuvanshi Loyal (5.3k points) | 2.8k views

0 votes

1 answer

9

computer organization and architecture
what is meaning of vectored interrupt... in vectored interrupt all device have separate interrupt request line or one single interrupt request line common for all io devices ? and what is the purpose of INTA signal?

answered 2 days ago in CO & Architecture by Shaik Masthan Boss (15.8k points) | 15 views

+21 votes

5 answers

10

GATE2014-1-43
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this $6$-stage pipeline, the speedup achieved with respect to non-pipelined execution if $25$% of the instructions incur $2$ pipeline stall cycles is ____________

answered 2 days ago in CO & Architecture by goxul Active (1.1k points) | 3.8k views

+6 votes

1 answer

11

Cache memory - Find Cache size ( given K, line size, tag memory, physical address space )

answered 2 days ago in CO & Architecture by Mk Utkarsh Boss (14k points) | 219 views

0 votes

0 answers

12

Two level of cache
Consider a two level cache system. For 100 memory references 20 misses in 1st level cache,10 misses in second level cache. Miss penalty from second level to memory is 40 cycles. if Total average = 7.6 cycles, then hit time of second level cache ? Assume hit time of second level cache is two times the first level cache? Ans. 4

asked 2 days ago in CO & Architecture by Na462 Active (4.5k points) | 61 views

+3 votes

4 answers

13

GATE2018-34
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$

answered 3 days ago in CO & Architecture by rohit vishkarma Junior (925 points) | 1.7k views

0 votes

1 answer

14

Explain this. And explain mapping. Just confuse between words per block. Per word n etc

answered 3 days ago in CO & Architecture by goxul Active (1.1k points) | 19 views

0 votes

0 answers

15

Computer organization

asked 3 days ago in CO & Architecture by BHASHKAR (11 points) | 42 views

0 votes

1 answer

16

test series

answered 3 days ago in CO & Architecture by Shivam Bhardwaj (319 points) | 105 views

+1 vote

0 answers

17

Addressing modes
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective ... required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?

asked 3 days ago in CO & Architecture by tusharp Junior (813 points) | 26 views

0 votes

1 answer

18

why comparator is used in Direct mapping technique,why can't we use simple And gate here?

answered 3 days ago in CO & Architecture by Mk Utkarsh Boss (14k points) | 65 views

0 votes

1 answer

19

Multilevel Cache Access time
Ans. A

answered 4 days ago in CO & Architecture by Mk Utkarsh Boss (14k points) | 45 views

0 votes

1 answer

20

Cache Capacity
if in a question it ask for cache capacity the is it calculated by follwing... cache capacity=cache size+ tag memory size+dirty bit cache capacity=tag bits * no. of cache lines which one is correct?

answered 4 days ago in CO & Architecture by Mk Utkarsh Boss (14k points) | 19 views

0 votes

0 answers

21

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked 5 days ago in CO & Architecture by Na462 Active (4.5k points) | 10 views

0 votes

0 answers

22

Control Memory

asked 5 days ago in CO & Architecture by Na462 Active (4.5k points) | 10 views

0 votes

0 answers

23

Test Series
Consider a processor uses 2 byte instruction format. Processor has 32 Registers and supports upto 2-Address instructions. If processor supports 128 1 Address instructions then number of 2-Address Instructions are? [closed]

asked 6 days ago in CO & Architecture by Manish Chetwani (291 points) | 22 views

+2 votes

1 answer

24

DMA Controller

answered 6 days ago in CO & Architecture by Mk Utkarsh Boss (14k points) | 77 views

0 votes

0 answers

25

carl hamacher(chapter 2 )
in the underline statement it is given that higher performance can be achieved if each instruction occupy one word???how it is true??what happen when two instruction occupy in single word???

asked Aug 11 in CO & Architecture by BASANT KUMAR Junior (799 points) | 15 views

0 votes

0 answers

26

harddisk
Consider magnetic disk with the following parameters: Average seek time = 12 ms Rotation rate = 3600 RPM Transfer rate = 3.5 MB/second # of Sectors per track = 64 Sector size =512 bytes Controller overhead =5.5 ms What is the average time to read 8 KB in ... only 8KB? Is it like same cylinder means no need to multiply by 16 and if given different cylinder then we need to consider 8kB*16?

asked Aug 11 in CO & Architecture by Amit puri Active (3k points) | 11 views

+3 votes

2 answers

27

Carl Hamcher
Assume that 20 percent of the dynamic count of the instructions executed for a program are branch instructions. Assume further that 75 percent of branches are actually taken. The program is executed in two different processors that have the same clock rate. ... ? (b) If the dynamic prediction accuracy is actually 90 percent, what is the speedup relative to using static prediction?

answered Aug 11 in CO & Architecture by Manish Chetwani (291 points) | 221 views

+2 votes

1 answer

28

Hamacher
7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possibility, the processor has a four stage pipeline and one delay slot, and in second possibility, ... the single delay slot. For the second alternative, the compiler is able to fill the second slot 25 percent of the time.

answered Aug 11 in CO & Architecture by Mk Utkarsh Boss (14k points) | 109 views

0 votes

1 answer

29

misses and hit
Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents number of compulsory and conflict misses?

answered Aug 10 in CO & Architecture by Shubhgupta Active (2.2k points) | 17 views

0 votes

0 answers

30

cache memory
Consider a cache of size 64 bytes, with block size 16 bytes and main memory is divided into blocks of 16 bytes each i.e. block 0 has address 0 to 15 so on. Consider the following program that access memory in given sequence: 1.Access address 63 through 70 2.Loop i) 15 ... line 0 contain address 0, 4, 8 etc. and line 1 contain address 1, 5, 7 etc. and so on.) [Upto 2 decimal places]

asked Aug 10 in CO & Architecture by Deepalitrapti (197 points) | 9 views

0 votes

0 answers

31

DMA Device
Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cycle take 2 μsec. What is the data transfer rate of DMA?

asked Aug 10 in CO & Architecture by Deepalitrapti (197 points) | 7 views

+3 votes

1 answer

32

Write a program that can evaluate the following expressions in single accumulator processor and stack base computer.

answered Aug 10 in CO & Architecture by ayush_karn (11 points) | 169 views

0 votes

1 answer

33

Cache Mapping
Consider a 16-way set associative cache which holds 64 KB of data. The size of physical address is of 40 bits. A cache block consist of 4 words. Every data word is of 32 bits. Assuming that all cache entries are initially empty and data words are word-addressable. Find the size of Tag , Set and Offset field in bits?

answered Aug 8 in CO & Architecture by Asutosh (359 points) | 6 views

0 votes

0 answers

34

test series
A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 106 instructions per second. An average instruction requires six processor cycles, three ... instruction per sec how? my assumption is in 1 sec both 95% and 5% of instruction should be executed .may i right or wrong ?

asked Aug 8 in CO & Architecture by Anshu Singh Suryavan (73 points) | 7 views

0 votes

1 answer

35

No. of Misses
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288

answered Aug 7 in CO & Architecture by Amit puri Active (3k points) | 26 views

0 votes

3 answers

36

Made Easy Test Series
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has ... 5+ (75+5-1)*3 Am i doing wrong? Solution with explanation of formulae being used will be welcomed.

answered Aug 7 in CO & Architecture by Amit puri Active (3k points) | 109 views

0 votes

0 answers

37

Addressing Mode
Consider the following expression used to execute on a stack CPU X = (A × B)+C, where all the variables are in the memory. What is the number of zero and one address instructions are required respectively to evaluate the expression?

asked Aug 7 in CO & Architecture by ben10 (131 points) | 10 views

0 votes

0 answers

38

test series
Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of the total instructions. If the miss penalty is 30 clock cycles and the miss rate is 4%, how much faster would the computer be if all instructions were cache hits?

asked Aug 6 in CO & Architecture by Anshu Singh Suryavan (73 points) | 3 views

0 votes

0 answers

39

Chip Select
Ans. C

asked Aug 6 in CO & Architecture by Na462 Active (4.5k points) | 8 views

+1 vote

0 answers

40

Signed 2's complement Exponent

asked Aug 6 in CO & Architecture by Na462 Active (4.5k points) | 17 views

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