Recent questions and answers in CO & Architecture

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1 answer

1

practice
Q1 A RAM chip has a capacity of 1024 words of 8 bits each(1K x 8).The number of 2 x 4 decoders with enable line needed to construct a 16k x 16 RAM from 1K x 8 RAM is A 4 B. 5 C 6 D.7 Q2 The contents of flag register after execution of following pgm by 8085 microprocessor will be SUB A MVI B,(01)H DCR B HTL A (54)H B(00)H C (01)H D(45)H

answered 4 days ago in CO & Architecture by arungate (369 points) | 25 views

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1 answer

2

effective access time
Should we have to include the time to access the frame also?

answered 5 days ago in CO & Architecture by sidlewis (189 points) | 141 views

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1 answer

3

Hamacher COA 5.7,p-362
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four 16-bit words, and each word has an associated 13-bit tag, as shown in Figure P5.2a. When a miss occurs during a read operation, the requested ... notation. The loop starts at location LOOP = 02EC Show the contents of the cache at the end of each pass through the loop.

answered 6 days ago in CO & Architecture by vupadhayayx86 (47 points) | 94 views

–1 vote

0 answers

4

Carl Hamacher Cache Memory
What should be correct answer to this question? In solution it's option A in Carl hamacher text book it's B ? I am confused please help

asked Jun 13 in CO & Architecture by vupadhayayx86 (47 points) | 61 views

0 votes

1 answer

5

about cache memory
For a system with two levels of cache, we define the following notation:  Tc1 = first-level cache access time  Tc2 = second-level cache access time  Tm = memory access time  H1 = first-level cache hit ratio  H2 = (first+second) level cache hit ratio. Provide an equation to calculate the average time of a read operation.

answered Jun 13 in CO & Architecture by Shaik Masthan Active (2.4k points) | 41 views

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1 answer

6

Branch Instruction
What is meaning of offset in Branch instruction? Is this offset same as conditional instruction offset? What is meaning of offset in virtual address? Where is actual difference between these two?

answered Jun 12 in CO & Architecture by Arunav Khare Active (5.1k points) | 27 views

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1 answer

7

Cache memory
Consider a scenario, where there is 2 level cache in a memory hierarchy. 1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instructions, then there will be 140 memory accesses. Here my question is how memory accesses can ... What miss rate is for L1,L2 and total in this memory hierarchy? Is it not number of misses in total number of instructions?

answered Jun 12 in CO & Architecture by Arunav Khare Active (5.1k points) | 34 views

0 votes

1 answer

8

Computer Organization - Pipelining
What are stage delays in pipelining? Are they nothing but execution time required for each stage? and 'After pipelining we have to adjust the stage delays such that no stage will be waiting for another to ensure smooth pipelining (continuous flow) ' What does this statement means? Please give a brief explanation.

answered Jun 9 in CO & Architecture by Deepakk Poonia (Dee) Boss (13.1k points) | 20 views

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9

Made Easy Test Series
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has ... 5+ (75+5-1)*3 Am i doing wrong? Solution with explanation of formulae being used will be welcomed.

asked Jun 9 in CO & Architecture by Subham Nagar Junior (539 points) | 34 views

0 votes

2 answers

10

pipelining
A CPU has five-stage pipeline where each stage takes 1ns, 2ns, 1.5ns, 3ns, 2.5ns. Instruction fetch happens in the first stage of the pipeline. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched ... one clock cycle. 30% of the instructions are conditional branches. Find the average execution time of the program for 1200 instructions is ________

answered Jun 8 in CO & Architecture by Soumya29 Loyal (9.7k points) | 69 views

0 votes

1 answer

11

Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?

answered Jun 7 in CO & Architecture by Deepakk Poonia (Dee) Boss (13.1k points) | 41 views

+47 votes

10 answers

12

GATE2016-2-30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement the computation $F(G(X_{i}))$ for $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

answered Jun 7 in CO & Architecture by kunal goswami (71 points) | 4.9k views

+36 votes

4 answers

13

GATE2017-1-51
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first ... ,129,257,129 \big \}$ is repeated $10$ times. The number of conflict misses experienced by the cache is _________ .

answered Jun 6 in CO & Architecture by kunal goswami (71 points) | 7.4k views

0 votes

0 answers

14

self doubt(carl hamacher,chapter1)
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of $500$ instruction including a $100$ instruction loop that is executed $25$ times.Determine the ratio of execution time without the cache to ... *24=7400$. my doubt is loop is occuring $25$ times so why there is multiplication of $24$ ??why not $25$??

asked Jun 4 in CO & Architecture by BASANT KUMAR (107 points) | 26 views

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0 answers

15

Computer organization and architecture 10th edition #Problems 14.11

asked Jun 4 in CO & Architecture by Aaron (7 points) | 34 views

0 votes

0 answers

16

Vectored Interrupts
Are Vectored Interrupts possible in CPU having single Interrupt Request line? How/Why not?

asked Jun 2 in CO & Architecture by Harsh Kumar (181 points) | 19 views

+1 vote

1 answer

17

UGCNET-Jan2017-II-34
The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing ‘SUB AL, BL’ assembly language instruction, are (1) AL = 0FH; CF = 1; SF = 1 (2) AL = F0H; CF = 0; SF = 0 (3) AL = F1H; CF = 1; SF = 1 (4) AL = 1FH; CF = 1; SF = 1

answered May 31 in CO & Architecture by BlueRose (17 points) | 248 views

0 votes

2 answers

18

Pipeline
Consider a 4 stage pipeline that consists of IF,ID,EX and WB stages.The time taken by these stages are 50ns,60ns,110ns and 80ns respectively.The pipeline registers are required after every pipeline stage and each of these pipeline registers consumes 10ns delay.What is the speedup of the pipeline under ideal conditions compare to the corresponding non-pipelined implementation?

answered May 31 in CO & Architecture by abhishekmehta4u Boss (14.3k points) | 46 views

0 votes

0 answers

19

WBUT 2012
A 30% enhancement in speedup for a component of the processor has been proposed for a new architecture.If the enhancement is usable only for 50% for the time,what is the fraction of the time must enhancement is used to achieve an overall speedup of 10?

asked May 31 in CO & Architecture by Sourav_35 (199 points) | 28 views

0 votes

1 answer

20

state exam
Program counter contains address of the Next programs to be fetched Previous programs to be fetched Previous information to be fetched Next information to be fetched

answered May 30 in CO & Architecture by Subarna Das Boss (10.5k points) | 57 views

0 votes

2 answers

21

#CO and Architecture
There is a $5$ stage Instruction pipeline, which takes $1$ $ns$ to execute each cycle. There are $4000$ branch instructions with a delay of $2$ clock cycles and $6000$ normal instructions ( They get completed in $5$ stages). What will be the total execution ... time for execution will be $6004 + 4006 = 10010$ $ns$ Is this a correct answer and right way to solve such problem?

answered May 30 in CO & Architecture by Anand. Active (1.2k points) | 82 views

0 votes

1 answer

22

carl Hamacher 6th edition Q.no 5.11
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction ... clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.

answered May 30 in CO & Architecture by Pawan Kumar 7 (29 points) | 200 views

0 votes

1 answer

23

expanding opcode technique
Can someone suggest a good video or link for ""expanding opcode technique""

answered May 29 in CO & Architecture by lokeshsolanki17 (123 points) | 299 views

0 votes

1 answer

24

ComputerOrganizationCarlHamacherChap4ExcerciseQ10

answered May 27 in CO & Architecture by vupadhayayx86 (47 points) | 38 views

0 votes

1 answer

25

Addressing mode

answered May 27 in CO & Architecture by Soumya29 Loyal (9.7k points) | 47 views

0 votes

0 answers

26

Expand opcode technique
The format of a double operand instructions of a cpu consist of $4$ bit opcode and $4$ bit for source and destination.$12$ double operand instructions and $24$ single operand instructions must be implemented.Opcode field must identify the three groups ... operand instructions .what is the total no. of zero operand instructions that can be implemented? $512$ $516$ $521$ $523$

asked May 26 in CO & Architecture by Prateek Raghuvanshi Active (3.9k points) | 128 views

0 votes

1 answer

27

Self doubt regarding instruction format
As we know in register to register reference cpu ,for transfer operation we use $LOAD$ and $STORE$ instruction .Both are $2 -$address instruction ,instead of these two ,can we use $MOV$ instruction?? ,which is also $2-$address instruction used in transfer the data between memory and register.

answered May 25 in CO & Architecture by Deepakk Poonia (Dee) Boss (13.1k points) | 38 views

0 votes

0 answers

28

Avg. Access Time
When we calculate avg access time, If it is not given in question like it is Hierarchal or Simultaneous access then by default we have to take which access to calculate avg access time?

asked May 25 in CO & Architecture by jatinkumar (203 points) | 36 views

+7 votes

2 answers

29

GATE2007-IT-37
Consider a Direct Mapped Cache with 8 cache blocks (numbered $0-7$). If the memory block requests are in the following order $3, 5, 2, 8, 0, 63, 9,16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82,17, 24.$ Which of the following memory blocks will not be in the cache at the end of the sequence ? $3$ $18$ $20$ $30$

answered May 25 in CO & Architecture by abhishekmehta4u Boss (14.3k points) | 808 views

0 votes

1 answer

30

Computer organisation
If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.

answered May 24 in CO & Architecture by Arunav Khare Active (5.1k points) | 60 views

+1 vote

1 answer

31

ISI-MTECH-PCB 2018

answered May 19 in CO & Architecture by Deepakk Poonia (Dee) Boss (13.1k points) | 91 views

+4 votes

3 answers

32

UGCNET-June2014-III-43
A byte addressable computer has a memory capacity of $2^{m}$ Kbytes and can perform $2^{n}$ operations. An instruction involving $3$ operands and one operator needs a maximum of $3m$ bits $m + n$ bits $3m + n$ bits $3m + n + 30$ bits

answered May 18 in CO & Architecture by Prasanjeet Ghosh Active (1.3k points) | 1.2k views

+1 vote

2 answers

33

UGCNET-Dec2014-III-05
How many times will the following loop be executed ? LXI B, 0007 H LOP : DCX B MOV A, B ORA C JNZ LOP $05$ $07$ $09$ $00$

answered May 17 in CO & Architecture by Girjesh Chouhan (141 points) | 857 views

+1 vote

3 answers

34

What is Byte Addressable and Word Addressable means in computer Architecture ? Difference between them with examples?

answered May 11 in CO & Architecture by gulsanchouhan (453 points) | 2.2k views

+1 vote

2 answers

35

ace test series
A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting ‘40’ number of two address instructions, ‘400' number of one address instructions. The maximum number of zero address instructions that can be formulated is

answered May 11 in CO & Architecture by abhishekmehta4u Boss (14.3k points) | 69 views

0 votes

1 answer

36

ace test series
Is Hardwire control system used for real time systems?

answered May 11 in CO & Architecture by abhishekmehta4u Boss (14.3k points) | 44 views

0 votes

2 answers

37

addressing modes

answered May 11 in CO & Architecture by pankaj_vir Loyal (8.5k points) | 53 views

0 votes

1 answer

38

ACE TEST SERIES
Is the statement true or false; "RISC type processor is designed with minimum number of processing registers" ?

answered May 11 in CO & Architecture by Deepakk Poonia (Dee) Boss (13.1k points) | 55 views

0 votes

0 answers

39

ISI 2016 C2 B
The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For execution of the programs, the system utilizes ... in-status, check-status, branch and read/write in memory, each requiring one machine cycle. Please explain the solution with details.

asked May 10 in CO & Architecture by MiNiPanda Loyal (5.8k points) | 20 views

0 votes

1 answer

40

Calculate time taken for disk access time

answered May 10 in CO & Architecture by amit1 Junior (635 points) | 59 views

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