Recent questions and answers in CO & Architecture

0 votes

1 answer

1

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

answered 14 hours ago in CO & Architecture by Da Tenshi ™ (23 points) | 227 views

–1 vote

0 answers

2

Self Doubt-Little/big endian-GeeksforGeeks
#include <stdio.h> int main() { unsigned char arr[2] = {0x01, 0x00}; unsigned short int x = *(unsigned short int *) arr; printf("%d", x); getchar(); return 0; } Output in little endian and big endian ? Please someone provide a detailed explanation if possible with diagram.

asked Jun 9 in CO & Architecture by Masterk (79 points) | 28 views

0 votes

1 answer

3

No of bits required to encode instructions
A computer has the following ISA and description - LOAD and STORE instructions capable of storing data from the accumulator to memory locations with indirect mode taking the argument as a register MOV capable of copying data from one register to another ADD ... 5 bit offset Min no of bits required to encode all the instructions above ?? Is it 4 bits ??

answered Jun 8 in CO & Architecture by Masterk (79 points) | 23 views

0 votes

1 answer

4

MadeEasy Test Series: CO & Architecture - Microprogramming

answered Jun 8 in CO & Architecture by Masterk (79 points) | 47 views

0 votes

1 answer

5

Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(

answered Jun 7 in CO & Architecture by harendra singh (25 points) | 30 views

0 votes

1 answer

6

NTA NET DEC 2018-53
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is- 0xC2006000 0xC2006666 0xC2206000 0xC2206666

answered Jun 7 in CO & Architecture by Ashwani Kumar 2 Boss (14.6k points) | 67 views

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0 answers

7

Indirect Addressing Mode
Consider an instruction of indirect addressing mode. What are the number of memory references by the processor when instruction is a computation that requires a single operand and when it is an unconditional branch instruction respectively ?? 3,3 3,2 2,2 4,3 I believe the answer is B Correct me

asked Jun 4 in CO & Architecture by s_dr_13 (119 points) | 15 views

+3 votes

2 answers

8

Interrupt
GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routine As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the ... am having confusion between option A and C... For hardware interrupt option A is suitable and for software interrupt option C

answered Jun 4 in CO & Architecture by Mk Utkarsh Boss (34.5k points) | 354 views

0 votes

1 answer

9

IEEE 754 Standard
In IEEE 754 single floating point format, how many numbers can be represented in the interval [10, 16)? A. B. 3 x 2^21 C. 5 X 2^21 D. 2^22

answered Jun 3 in CO & Architecture by prashant jha 1 Loyal (5.5k points) | 32 views

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0 answers

10

Bits HD 2019
In a microprocessor, size of register is generally: Lesser than the size of the data it operates on Greater than the size of the data it operates on Equal to the size of the data it operates on

asked May 29 in CO & Architecture by manikgupta123 (75 points) | 35 views

0 votes

3 answers

11

MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)

answered May 29 in CO & Architecture by juuniversity (25 points) | 236 views

0 votes

1 answer

12

RISC JUMP INSTRUCTION SELF DOUBT
Why can’t we keep target32 address in the 32 bit registers of the RISC instruction? Why is it have to be t J target26 instead of J target32 ?

answered May 29 in CO & Architecture by Anuj Mishra Active (1.9k points) | 22 views

+3 votes

1 answer

13

Average Number of stalls
Consider a CPU contains 2000 instructions, there are 80 misses in the L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and ... 0.95 * 0 {As there is no stalls when hit in L1 cache} + 0.05(30 + 0.5 * 200) 6.5 stalls/instruction.

answered May 25 in CO & Architecture by juuniversity (25 points) | 210 views

0 votes

2 answers

14

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

answered May 25 in CO & Architecture by abhishekmehta4u Boss (33.9k points) | 46 views

+1 vote

1 answer

15

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

answered May 23 in CO & Architecture by Satbir Boss (12.9k points) | 39 views

0 votes

0 answers

16

Number System (self doubts)
mam how convert into hexadecimal

asked May 22 in CO & Architecture by altamash (389 points) | 17 views

0 votes

2 answers

17

Carl hamacher
A program consists of two nested loops-a small inner loop and a much larger outer loop.The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections of ... the cycle time of the cache is 1τ s. Compute the total time needed for instruction fetching during execution of the program.

answered May 21 in CO & Architecture by isilia (11 points) | 214 views

0 votes

0 answers

18

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

asked May 21 in CO & Architecture by Ritabrata Dey (29 points) | 19 views

+43 votes

3 answers

19

GATE2004-63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ \begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\ ... halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$

answered May 21 in CO & Architecture by Apoorv Singh (13 points) | 8.2k views

0 votes

0 answers

20

ROM(self doubts)
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits)

asked May 19 in CO & Architecture by altamash (389 points) | 12 views

+2 votes

1 answer

21

Cache Average access time
So as we know there are 2 different approaches for cache.. Sequential and the Hierarchical. Exactly which formula should I use when only access times and hit ratio is mentioned in case of 2 level memory system..? It would be great if someone explains how to approach questions related to average access time.

answered May 19 in CO & Architecture by Hirak Active (3k points) | 106 views

0 votes

2 answers

22

Direct Mapped Cache Multiplexer
Is there any multiplexer(s) present in the implementation of Direct Mapped Cache? If yes, then the Hit latency would be Multiplexer latency + Comparator Latency?

answered May 17 in CO & Architecture by !KARAN Active (1.8k points) | 73 views

0 votes

0 answers

23

set associative (carl hamacher)
Block set associative cache consists of a total of 64blocks divided into 4blocks sets .The main memory contains 4096blocks ,each consisting of 128 words. how many bits for Main memory how many bits for TAG,SET,WORD . solution: MM=block size*words 2^12 * 2^7=19 bits TAG=9 SET=4 WORD=6 is this correct method or not please correct me

asked May 13 in CO & Architecture by altamash (389 points) | 18 views

0 votes

0 answers

24

No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.

asked May 7 in CO & Architecture by Tuhin Dutta Loyal (9k points) | 41 views

+3 votes

3 answers

25

UGCNET-June2016-III-5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement

answered May 7 in CO & Architecture by Kuljeet Shan Active (1.4k points) | 1.5k views

+20 votes

3 answers

26

GATE2006-IT-40
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ respectively before the following program is executed. $\begin{array}{ll} \text{MOVI} & \text{$R_s, 1$} && \text{; Move immediate} \\ \text{LOAD} & \text{$R_d ... $20$ Memory location $1020$ has value $20$ Memory location $1021$ has value $20$ Memory location $1001$ has value $20$

answered Apr 29 in CO & Architecture by Sambhrant Maurya Active (1.4k points) | 2.4k views

0 votes

1 answer

27

IIIT PGEE 2019
Which part in 8086 microprocessor is responsible for fetching instructions into the queue? BIU EU Stack Registers

answered Apr 29 in CO & Architecture by gaurav1.yuva (427 points) | 63 views

0 votes

0 answers

28

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked Apr 17 in CO & Architecture by srestha Veteran (111k points) | 46 views

0 votes

1 answer

29

which book should i refer to cover all the concept of cache memory and memory hierarchy in CO and Architecture.

answered Apr 17 in CO & Architecture by rajabhardwajrai (15 points) | 68 views

0 votes

0 answers

30

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked Apr 16 in CO & Architecture by Ritabrata Dey (29 points) | 22 views

0 votes

0 answers

31

Goldman Sachs Screening Test
In Matrix Multiplication Operation Code uses Temporal Locality and Data uses Spatial Locality Data uses Temporal Locality and Code uses Spatial Locality Both data and code uses Spatial Locality Both data and code uses Temporal Locality

asked Apr 14 in CO & Architecture by ved (5 points) | 14 views

0 votes

0 answers

32

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12 in CO & Architecture by Miny (139 points) | 5 views

+14 votes

3 answers

33

GATE2015-2-24
Assume that for a certain processor, a read request takes $50$ $nanoseconds$ on a cache miss and $5$ $nanoseconds$ on a cache hit. Suppose while running a program, it was observed that $80$% of the processor's read requests result in a cache hit. The average read access time in nanoseconds is _____.

answered Apr 9 in CO & Architecture by Rishi yadav Boss (10.5k points) | 3.6k views

+24 votes

4 answers

34

GATE2008-IT-38
Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address ... back to the stack. ADD (X)−, (X) ADD (X), (X)− ADD −(X), (X)+ ADD −(X), (X)

answered Apr 7 in CO & Architecture by Divy Kala Junior (677 points) | 2.8k views

+28 votes

5 answers

35

GATE2008-72
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; /* ... elements have the same cache index as $ARR[0][0]$? $ARR[0][4]$ $ARR[4][0]$ $ARR[0][5]$ $ARR[5][0]$

answered Apr 5 in CO & Architecture by Piyush #### (55 points) | 3.2k views

+1 vote

3 answers

36

Madeeasy Test Series
Suppose that in 1000 memory references there are 150 misses in first level and 100 misses in second level cache. Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles. If there are 4 memory references per instruction, the average stall per instruction is

answered Apr 5 in CO & Architecture by Sahil Arora (27 points) | 671 views

+2 votes

1 answer

37

average memory access time
The access time of cache memory is 45 nsec and that of main memory is 750 nsec. It is found that 75% of memory requests are for read and remaining for write. If the hit access for read is 0.9 and hit ratio for write is 1 and write through protocol is used, then the average memory access time is ________.

answered Apr 2 in CO & Architecture by Hiral Rajgor (17 points) | 469 views

+1 vote

6 answers

38

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

answered Apr 2 in CO & Architecture by Àbhíjèét Míshrà (79 points) | 3.4k views

0 votes

0 answers

39

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2 in CO & Architecture by srestha Veteran (111k points) | 42 views

0 votes

1 answer

40

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

answered Apr 1 in CO & Architecture by abhishekmehta4u Boss (33.9k points) | 64 views

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