Recent questions and answers in CO and Architecture - GATE Overflow

+17 votes

4 answers

1

GATE2016-2-10
A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.

answered 10 hours ago in CO and Architecture by shivam001 Junior (611 points) | 3.2k views

+22 votes

5 answers

2

GATE2007-72
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... memory is word addressable. After the execution of this program, the content of memory location $2010$ is: $100$ $101$ $102$ $110$

answered 17 hours ago in CO and Architecture by shivam001 Junior (611 points) | 2.5k views

+3 votes

2 answers

3

ISRO2011-42
The search concept used in associative memory is Parallel search Sequential search Binary search Selection search

answered 18 hours ago in CO and Architecture by JashanArora Active (1.7k points) | 2.6k views

+1 vote

4 answers

4

ISRO2011-41
If a microcomputer operates at 5 MHz with an 8-bit bus and a newer version operates at 20 MHz with a 32-bit bus, the maximum speed-up possible approximately will be 2 4 8 16

answered 19 hours ago in CO and Architecture by JashanArora Active (1.7k points) | 2.4k views

0 votes

1 answer

5

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the following statements: (i) Accessing of data in a column wise fashion maintains spatial locality only when the block size is equal to the total size of the elements in the row (ii) Coherence in write through protocol never occurs even cache memory is organized in multilevel. Which of the above is true?

answered 1 day ago in CO and Architecture by kunal goswami Junior (533 points) | 65 views

+81 votes

4 answers

6

GATE2005-68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register ... cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

answered 2 days ago in CO and Architecture by AkshayBatheja1996 (15 points) | 13.8k views

0 votes

1 answer

7

self doubt
Main memory=512 words. block size=8 words. cache size =32 words what is tag,line no.,block offset bits

answered 2 days ago in CO and Architecture by Saideepak Bejawada (425 points) | 64 views

+3 votes

3 answers

8

ISRO2008-55
The Memory Address Register is a hardware memory device which denotes the location of the current instruction being executed. is a group of electrical ckt, that performs the intent of instructions fetched from memory contains the address of the memory location that ... location specified by the MAR after a "read" or the new contents of the memory prior to a "write"

answered 2 days ago in CO and Architecture by JashanArora Active (1.7k points) | 1.2k views

+1 vote

4 answers

9

ISRO2008-37
The ability to temporarily halt the CPU and use this time to send information on buses is called direct memory access vectoring the interrupt polling cycle stealing

answered 2 days ago in CO and Architecture by JashanArora Active (1.7k points) | 1.8k views

+5 votes

3 answers

10

ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt

answered 2 days ago in CO and Architecture by JashanArora Active (1.7k points) | 1.9k views

+6 votes

6 answers

11

ISRO-2013-15
A pipeline $P$ operating at $400$ MHz has a speedup factor of $6$ and operating at $70$% efficiency. How many stages are there in the pipeline? $5$ $6$ $8$ $9$

answered 4 days ago in CO and Architecture by JashanArora Active (1.7k points) | 4k views

+9 votes

4 answers

12

ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time will the processor be slowed down due to DMA activity? $9.6$ms $4.8$ms $2.4$ms $1.2$ms

answered 4 days ago in CO and Architecture by JashanArora Active (1.7k points) | 3.5k views

0 votes

1 answer

13

Virtual Gate Test Series: CO & Architecture - Pipelining
Consider the unpipelined machine with $10$ ... overhead to the clock. _____________ times speed up in the instruction execution rate is gained from a pipeline.

answered 4 days ago in CO and Architecture by vikramjee96 (51 points) | 54 views

+2 votes

7 answers

14

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

answered 5 days ago in CO and Architecture by JashanArora Active (1.7k points) | 4k views

0 votes

2 answers

15

UGCNET-June2015-II-46-Parallel-processing
In the case of parallelization, Amdahl's law states that if P is the proportion of a program that can be made parallel and (1-P) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is: $\frac{1}{(1-P)+N.P}$ $\frac{1}{(N-1)P+P}$ $\frac{1}{(1-P)+\frac{P}{N}}$ $\frac{1}{P+\frac{(1-P)}{N}}$

answered 6 days ago in CO and Architecture by deenanathgupta (103 points) | 802 views

+1 vote

2 answers

16

UGCNET-Nov2017-iii-3
In the architecture of 8085 microprocessor match the following : (a) Processing Unit (i) Interrupt (b) Instruction unit (ii) General Purpose Register (c) Storage and Interface unit (iii) ALU (iv) Timing and Control Code: (a) (b) (c) A. (iv) (i) (ii) B. (iii) (iv) (ii) C. (ii) (iii) (i) D. (i) (ii) (iv)

answered 6 days ago in CO and Architecture by deenanathgupta (103 points) | 496 views

+4 votes

2 answers

17

pipeline
Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations and 5 cycles for branches and 4 cycles for memory operations. Assume that the relative frequencies of these operations are 50 %, 35 % and ... overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline?

answered 6 days ago in CO and Architecture by Pradosh123 (11 points) | 1.7k views

0 votes

1 answer

18

GATE 1995
If the disk is rotating at 3600rpm, determine the effective data transfer rate at which is defined as the number of bytes transfered per second between disk and memory. (Given size of track = 512 bytes)?

answered Nov 28 in CO and Architecture by Ayan Kumar Pahari (193 points) | 131 views

+1 vote

1 answer

19

ISRO2012-ECE: Computer Architecture
The register in 8085 that is used to keep track of the memory address of the next opcode to be run in the program is the: a) Stack Pointer b) Program Counter c) Accumulator d) Non of the above

answered Nov 22 in CO and Architecture by tron46 (21 points) | 105 views

+35 votes

10 answers

20

GATE2016-2-50
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to read a block from the disk is $10$ ms. Assume that the cost of checking ... are in multiples of $10$ MB. The smallest cache size required to ensure an average read latency of less than $6$ ms is _________ MB.

answered Nov 22 in CO and Architecture by King Suleiman Junior (979 points) | 4.9k views

+1 vote

4 answers

21

UGCNET-June-2019-II-19
How many address lines and data lines are required to provide a memory capacity of $16 K \times 16$? $10, \:4$ $16, \: 16$ $14, \:16$ $4, \:16$

answered Nov 22 in CO and Architecture by tron46 (21 points) | 269 views

0 votes

1 answer

22

Self-doubt
What is actually meant by average access time experienced by processor?

answered Nov 22 in CO and Architecture by Saideepak Bejawada (425 points) | 24 views

0 votes

1 answer

23

ME-Practice Book COA Q#48

answered Nov 21 in CO and Architecture by GATE2021 (37 points) | 40 views

+23 votes

3 answers

24

GATE2003-10, ISRO-DEC2017-41
For a pipelined CPU with a single ALU, consider the following situations The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand The execution of a conditional jump instruction The $j^{th}$ and ${j+1}^{st}$ instructions ... the ALU at the same time. Which of the above can cause a hazard I and II only II and III only III only All the three

answered Nov 20 in CO and Architecture by Praveenk99 (49 points) | 3.1k views

+3 votes

3 answers

25

MadeEasy Subject Test 2019: CO & Architecture - Pipelining
Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?

answered Nov 19 in CO and Architecture by MRINMOY_HALDER Active (3k points) | 494 views

0 votes

2 answers

26

Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.

answered Nov 19 in CO and Architecture by MRINMOY_HALDER Active (3k points) | 184 views

0 votes

3 answers

27

Ace Test Series: CO & Architecture - SpeedUp In Pipeline
Consider a nonpipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is

answered Nov 19 in CO and Architecture by MRINMOY_HALDER Active (3k points) | 317 views

0 votes

1 answer

28

processor performance
insufficient info p2 p1

answered Nov 19 in CO and Architecture by Sumit Singh Chauhan Active (1.5k points) | 40 views

+5 votes

2 answers

29

mock gate COA
A nonpipelined processor operating at 1 MHz is converted into a synchronous pipelined processor with five stages requiring 3.5 μsec, 2.5 μsec, 3 μsec, 2.5 μsec and 3.5 μsec, respectively. The delay of the latches is 1 μsec. The speedup of the pipeline processor for a large number of ... ans is 3.33 speedup =(3.5+2.5+3+2.5+3.5)/4.5 =3.33 why my ans is wrong ? please explain

answered Nov 19 in CO and Architecture by mohan123 Active (1.3k points) | 116 views

0 votes

1 answer

30

made easy test series
please provide a detailed solution

answered Nov 18 in CO and Architecture by SaurabhKatkar (149 points) | 73 views

+81 votes

10 answers

31

GATE2004-47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The ... instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

answered Nov 18 in CO and Architecture by Doraemon Junior (729 points) | 20.2k views

+2 votes

2 answers

32

UGCNET-June2012-III-5
Suppose that the given application is run on a 64-processor machine and that 70 percent of the application can be parallelized. Then the expected performance improvement using Amdahl’s law is 4.22 3.22 3.32 3.52

answered Nov 15 in CO and Architecture by Gaurishankar Acharya (61 points) | 1.6k views

+1 vote

1 answer

33

Ace Test Series: CO & Architecture - Instruction Execution
CPU can leave current instruction execution, without completing it for : Service of interrupt DMA Both Neither

answered Nov 15 in CO and Architecture by mahabir10 (177 points) | 102 views

+25 votes

4 answers

34

GATE2017-1-11
Consider the $C$ struct defined below: struct data { int marks [100]; char grade; int cnumber; }; struct data student; The base address of student is available in register $R1$. The field student.grade can be accessed efficiently using: Post-increment addressing mode ... $R1$ Index addressing mode, $X(R1)$, where $X$ is an offset represented in $2's$ complement $16-bit$ representation

answered Nov 15 in CO and Architecture by King Suleiman Junior (979 points) | 4.2k views

+31 votes

3 answers

35

GATE2017-1-49
Consider a RISC machine where each instruction is exactly $4$ bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with ... $i,$ then the decimal value of the Offset is ____________ .

answered Nov 14 in CO and Architecture by King Suleiman Junior (979 points) | 4.2k views

+6 votes

3 answers

36

Pipeline
Consider a pipeline x' consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns. The alternative pipeline y' contain the same number of stages but EX stage is divided into ... contains 30% of the instructions which are memory based instructions, the ratio of the speedup ratio of x to the speedup ratio of y is ___________.

answered Nov 13 in CO and Architecture by blackcloud (257 points) | 702 views

0 votes

2 answers

37

cache memory
Suppose after analyzing a new cache design, you discover that the cache has far too many conflict misses and this needs to be resolved. You know that you must increase associativity in order to decrease the number of cache misses. What are the implications of increasing associativity? (a) Slower cache access time (b) Increase index bits (c) Increase block size (d) All of these

answered Nov 11 in CO and Architecture by blackcloud (257 points) | 420 views

+1 vote

1 answer

38

Doubt on associativity
Does increasing cache associativity decreases conflict misses?

answered Nov 11 in CO and Architecture by PRG1499 (27 points) | 44 views

+47 votes

9 answers

39

GATE2007-80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main memory starting ... the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$

answered Nov 8 in CO and Architecture by dharmesh7 Active (1.2k points) | 8.9k views

+3 votes

2 answers

40

Compiler Design: Viable Prefix
Consider the following grammar:- A string (id + id ∗ id) is parsed using above grammar. Which of the following statement is correct with respect to above parsing? a. “E+F ∗” is a viable prefix b. “E+F ∗” is a handle c. “T ∗ F” is a viable prefix d. “T ∗ F” is not a handle Answer is (a). Can any one tell me what are viable prefix and how to identify them.

answered Nov 8 in CO and Architecture by srestha Veteran (117k points) | 483 views

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