Recent questions and answers in CO and Architecture

0 votes

0 answers

1

Morris Mano
The binary numbers listed have a sign in the leftmost position and if negative, are in 2’s complement form. Perform the arithmetic operations indicated and verify: (a) 101011+ 111000 (b) 001110+110010 (c ) 111001-001010 (d) 101011-100110

lakshaymittal asked in CO and Architecture 21 hours ago

by lakshaymittal

14 views

0 votes

0 answers

2

Computer Organization, Instruction Set Architecture, Gateforum
Consider a system with 16 Registers(Ro,R1,...R8).An instruction SUB Ro,R1 , which is two bytes long,what is the space assigned to the opcode field (in bits) ?

Swarnava Bose asked in CO and Architecture 21 hours ago

by Swarnava Bose

11 views

1 vote

1 answer

3

#Doubt on Microprocessor and cpu
I want to confirm the exact difference between a cpu and microprocessor and also between microprocessor and microcontroller.Anyone pls explain!

Awe111 answered in CO and Architecture Oct 13

by Awe111

26 views

43 votes

7 answers

4

GATE CSE 2007 | Question: 54
In a simplified computer the instructions are: $\begin{array}{|l|l|} \hline \text {OP $R _j , R _i$} & \text{Perform $R _j $OP $R _i$ and store the result in register $R _j$ } \\\hline \text{OP $ ... computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block? $2$ $3$ $5$ $6$

Mohitdas answered in CO and Architecture Oct 11

8.7k views

44 votes

5 answers

5

GATE IT 2007 | Question: 41
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. ... to execute the above code segment assuming each instruction takes one cycle to execute? $7$ $10$ $13$ $14$

Mohitdas answered in CO and Architecture Oct 11

9.5k views

0 votes

1 answer

6

Pearson Gate 2022 CSE , Computer Organization and Architecture, Chapter 2 , Question 17, Page 2.28

Codered03 answered in CO and Architecture Oct 11

73 views

1 vote

2 answers

7

ISI2014-PCB-CS-5
The average memory access time for a microprocessor with first level cache is $3$ clock cycles. If data is present in the cache, it is found in $1$ clock cycle. If data is not found in the cache, $100$ clock cycles are needed to get it from off-chip ... $20 \%$ of the total execution time, respectively. Calculate the overall speed-up of $P$ when it is executed on the new machine.

sridhar15399 answered in CO and Architecture Oct 9

by sridhar15399

353 views

1 vote

5 answers

8

Instruction Execution
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in ... for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18

Mohitdas answered in CO and Architecture Oct 8

1.1k views

3 votes

1 answer

9

Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____

Yaman Sahu answered in CO and Architecture Oct 8

61 views

3 votes

3 answers

10

GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ ... . Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________

Mohitdas answered in CO and Architecture Oct 8

1.7k views

1 vote

1 answer

11

Nptel Assignment Question
The instruction $LDA$ $FF0$ (machine code of $LDA$ is $5$) is stored in location $7F0$. The contents in memory location $FF0$ are loaded into accumulator. After its execution, accumulator stores value $8$. The figure below shows a snapshot of the registers and their contents. ... $MAR = 7F0$, $IR = 5FF0$, $MBR = 5FF0$ $MAR = FF1$, $IR = 5FF0$, $MBR = 7F0$

Codered03 answered in CO and Architecture Oct 7

61 views

1 vote

0 answers

12

4 Address Instruction
Where are 4 Address Instructions are used and how?

prashastinama asked in CO and Architecture Oct 3

by prashastinama

44 views

4 votes

3 answers

13

GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ ... $\text{DMA}$, the data transfer rate of the device is __________ bits per second.

manikantsharma answered in CO and Architecture Sep 22

by manikantsharma

2.1k views

0 votes

0 answers

14

William Stallings - Computer Organization and Architecture D
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . . ... from the use of the cache. Assume an LRU policy for block replacement. Show the state of cache at the end.

lucifer069 asked in CO and Architecture Sep 16

48 views

0 votes

0 answers

15

William Stallings - Computer Organization and Architecture D
Consider the following assembly code: Instruction Description LD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, R1, R5 Add contents of R1 ... Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.

lucifer069 asked in CO and Architecture Sep 16

41 views

39 votes

5 answers

16

GATE CSE 2006 | Question: 43
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction bbs reg, pos, label jumps to label if bit in position pos of register operand reg is one. A register is $32$ -bits wide and the bits are numbered $0$ to $31,$ bit ... $ mask\leftarrow \text{0xffffffff} << pos$ $ mask\leftarrow pos $ $ mask\leftarrow \text{0xf}$

milinbhade answered in CO and Architecture Sep 14

6.9k views

44 votes

6 answers

17

GATE CSE 2008 | Question: 77
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4

abhi97.dutta answered in CO and Architecture Sep 14

by abhi97.dutta

8.4k views

0 votes

1 answer

18

Self-doubt
In floating point representations , how to determine what is to be subtracted from the exponent ? In 32 bit representation, somewhere it is said to subtract 128 from the exponent, somewhere it is written 127 to be subtracted ? How to check this ?

Anilsapkal answered in CO and Architecture Sep 10

167 views

0 votes

1 answer

19

Structure of control word in control memory
What is the structure of control word for Horizantal microprogrammed control unit? <Conditional branch bit, flag bits, contol field, next address> OR <log(Conditional branch bits), log(flag bits), contol field, next address>

saykatamkeen answered in CO and Architecture Sep 7

by saykatamkeen

60 views

30 votes

6 answers

20

GATE CSE 1996 | Question: 2.25
A micro program control unit is required to generate a total of $25$ control signals. Assume that during any micro instruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be: $2$ $2.5$ $10$ $12$

jaswanth431 answered in CO and Architecture Sep 7

17.7k views

0 votes

1 answer

21

Morris Mano [COA]
Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. S Cin = 0 Cin = 1 0 D= A+B (add) D= A+1 (increment) 1 D= A-1 (decrement) D= A+B′+1 (subtract)

Mohammed Hussain answered in CO and Architecture Sep 6

by Mohammed Hussain

1.2k views

1 vote

1 answer

22

How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2. How will the carry and zero flags we be modified after above instruction is executed? Case 1: R1< R2 Carry Flag = 1 Zero Flag = 0 R1= R2 Carry Flag = 0 Zero Flag = 1 R1> R2 ... 0 Zero Flag = 1 R1> R2 Carry Flag = 1 Zero Flag = 0 Which one of the above two cases is correct?

saxena0612 answered in CO and Architecture Sep 5

66 views

20 votes

4 answers

23

GATE CSE 1994 | Question: 12
Assume that a CPU has only two registers $R_1$ and $R_2$ and that only the following instruction is available $XOR \: R_i, R_j;\{R_j \leftarrow R_i \oplus R_j, \text{ for } i, j =1, 2\}$ Using this XOR instruction, find an instruction sequence in ... and $R_2$ The line p of the circuit shown in figure has stuck at $1$ fault. Determine an input test to detect the fault.

jaswanth431 answered in CO and Architecture Sep 5

2.3k views

35 votes

10 answers

24

GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec

HitechGa answered in CO and Architecture Aug 26

12k views

0 votes

4 answers

25

GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.

K2 answered in CO and Architecture Jul 31

by K2

1.1k views

8 votes

3 answers

26

GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________

K2 answered in CO and Architecture Jul 31

by K2

3k views

5 votes

4 answers

27

GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________

K2 answered in CO and Architecture Jul 31

by K2

1.7k views

2 votes

2 answers

28

Split Phase of Pipelining
Can anybody explain the concept of Split phase (2 stages in same clock-cycle) in Pipelining Briefly. i.e. When to use,How to use and Advantages.

Intekhab Ahmad answered in CO and Architecture Jul 31

by Intekhab Ahmad

849 views

61 votes

4 answers

29

GATE CSE 2004 | Question: 63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$

madhes23 answered in CO and Architecture Jul 30

18.7k views

38 votes

5 answers

30

GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode

Gaurav Yadav answered in CO and Architecture Jul 27

by Gaurav Yadav

9.5k views

24 votes

5 answers

31

GATE CSE 2019 | Question: 2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF

aloksingh017 answered in CO and Architecture Jul 16

by aloksingh017

8.2k views

18 votes

8 answers

32

GATE CSE 2019 | Question: 1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses ... $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

aloksingh017 answered in CO and Architecture Jul 16

by aloksingh017

11.3k views

1 vote

2 answers

33

ISI-JRF
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).

rish1602 answered in CO and Architecture Jul 14

418 views

1 vote

2 answers

34

anupam_yedida answered in CO and Architecture Jul 11

by anupam_yedida

515 views

2 votes

5 answers

35

ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing

Harshad_Shinde answered in CO and Architecture Jul 8

by Harshad_Shinde

1.9k views

5 votes

3 answers

36

IEEE 754 Standard
In IEEE $754$ single floating point format, how many numbers can be represented in the interval [10, 16)? A. $2^{21}$ B. $3 * 2^{21}$ C. $5 * 2^{21}$ D. $2^{22}$

rish1602 answered in CO and Architecture Jun 27

998 views

36 votes

4 answers

37

GATE CSE 2013 | Question: 28
Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence? Instruction fetch Operand fetch Conditional branch Initiation of interrupt service

sridhar15399 answered in CO and Architecture Jun 23

by sridhar15399

9.7k views

44 votes

7 answers

38

GATE CSE 2014 Set 1 | Question: 55
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $\text{25%}$ less time but incurs $\text{20%}$ more CPI (clock cycles per instruction) ... If the clock frequency of $P_1$ is $\text{1GHZ}$, then the clock frequency of $P_2$ (in GHz) is ______.

ShivangiChauhan answered in CO and Architecture Jun 21

by ShivangiChauhan

12.2k views

1 vote

2 answers

39

Word Addressable (GATE 2004)

TusharSNagpal answered in CO and Architecture Jun 17

by TusharSNagpal

875 views

0 votes

2 answers

40

AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.

meentu answered in CO and Architecture Jun 13

by meentu

376 views

To see more, click for all the questions in this category.

Follow @gateoverflow

GATE Overflow

Recent questions and answers in CO and Architecture

Search GATE Overflow