Recent questions and answers in CO & Architecture

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0 answers

1

Refresh overhead
Explain the refresh overhead in dram?

asked 9 hours ago in CO & Architecture by Mayank Gupta 3 (463 points) | 3 views

+1 vote

2 answers

2

GATEBOOK-2019-COA2-8
Consider a database server which handles search queries with double indirect pointers, $88\%$ of its total active query handling time. An improvement is made and the indirection is removed with direct pointers which caused the search query handling time to be enhanced by $2000\%$. The overall speedup is: $4.33$ $6.1$ $9.5$ $12.6$

answered 9 hours ago in CO & Architecture by Arjun Veteran (369k points) | 38 views

0 votes

0 answers

3

Register renamimg
Give an example where register renamimg helps in eliminating the hazards

asked 11 hours ago in CO & Architecture by Mayank Gupta 3 (463 points) | 7 views

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0 answers

4

SELF DOUBT
https://gateoverflow.in/61144/ugcnet-june2015-iii-5 NOT GETTING AT LAST …….

asked 11 hours ago in CO & Architecture by eyeamgj Loyal (6.3k points) | 6 views

0 votes

0 answers

5

DMA and Interrupt mechanism
DMA does issue an interrupt for bus request after the transfer is complete from I/O device to disk(i.e. after the preparation time) right ?

asked 11 hours ago in CO & Architecture by Ashwani Yadav (399 points) | 10 views

+9 votes

2 answers

6

GATE2002-2.7
Horizontal microprogramming: does not require use of signal decoders results in larger sized microinstructions than vertical microprogramming uses one bit for each control signal all of the above

answered 12 hours ago in CO & Architecture by Suneel Padala (139 points) | 1.8k views

+1 vote

2 answers

7

Refresh rate of memory
Consider a DRAM that must be given a refresh cycle 64 times per msec. Each refresh operation require 100 nsec and a memory cycle require 200 nsec. The percentage of the memory’s total operating time must be given to refresh is ________. (Upto 2 decimal places)

answered 14 hours ago in CO & Architecture by chauhansunil20th Active (1.9k points) | 83 views

0 votes

0 answers

8

Testbook subject test
what is the meaning of assertion.I know PC requires 1 memory access but they said 2.

asked 16 hours ago in CO & Architecture by Mayank Gupta 3 (463 points) | 8 views

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0 answers

9

TESTBOOK COA

asked 16 hours ago in CO & Architecture by Mayank Gupta 3 (463 points) | 14 views

+17 votes

2 answers

10

GATE2001-2.9
Which is the most appropriate match for the items in the first column with the items in the second column: X. Indirect Addressing I. Array implementation Y. Indexed addressing II. Writing relocatable code Z. Base Register Addressing III. Passing array as parameter (X, III), (Y, I), (Z, II) (X, II), (Y, III), (Z, I) (X, III), (Y, II), (Z, I) (X, I), (Y, III), (Z, II)

answered 20 hours ago in CO & Architecture by Suneel Padala (139 points) | 1.4k views

0 votes

0 answers

11

Self Doubt
How to find the number of mux required in a k-way set associative cache? Please give the implementation of the same.

asked 20 hours ago in CO & Architecture by Vipin Rai (389 points) | 9 views

0 votes

0 answers

12

made easy test series
consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and there are 1.8 memory references per instruction, then average stall per instruction is 6.36 7.92 9.62 9.35

asked 21 hours ago in CO & Architecture by scarz (19 points) | 17 views

+1 vote

2 answers

13

GATEBOOK-2019-COA2-20
In a $32$-bit computer instruction format, the size of address field is $9$-bits. The computer uses expanding opcode technique and has $28$ three-address instructions, $2040$ two-address instructions, $4040$ one-address instructions. The number of zero-address instructions it can support is ________

answered 1 day ago in CO & Architecture by Manoja Rajalakshmi A Loyal (6.3k points) | 35 views

+9 votes

5 answers

14

GATE2018-34
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$

answered 1 day ago in CO & Architecture by Ashwani Kumar 2 Boss (12.3k points) | 2.1k views

0 votes

1 answer

15

pipelining
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 25% of the time for 1 cycle and 10% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI ?(ans=2.05)

answered 1 day ago in CO & Architecture by Rishabh Agrawal (401 points) | 37 views

0 votes

0 answers

16

Hard disk data transfer rate , data rate

asked 1 day ago in CO & Architecture by Mayank Gupta 3 (463 points) | 13 views

0 votes

0 answers

17

Cache organisation
Do we use multiplexer in direct mapped cache ?

asked 1 day ago in CO & Architecture by Mayank Gupta 3 (463 points) | 11 views

0 votes

0 answers

18

ace Q

asked 1 day ago in CO & Architecture by kallu singh Junior (937 points) | 16 views

0 votes

0 answers

19

AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.

asked 2 days ago in CO & Architecture by shaz (171 points) | 20 views

0 votes

0 answers

20

Seek Time
According to the specification of a particular hard disk seek time takes 3 milliseconds between adjacent tracks. If the disk has 100 tracks how long will it take from for the head to move from innermost most cylinder to the outermost cylinder?

asked 2 days ago in CO & Architecture by RohitKumarSingh (35 points) | 9 views

0 votes

0 answers

21

Memory Hierarchy (Made easy Test Series)

asked 2 days ago in CO & Architecture by Na462 Loyal (7.5k points) | 12 views

+2 votes

1 answer

22

ME TEST SERIES
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is ________. 100, 108, 114, 1C7, 128, 1B5, 100, 108, 1C7

answered 2 days ago in CO & Architecture by Prateek Raghuvanshi Loyal (8k points) | 124 views

0 votes

0 answers

23

memory write
why data Bus is not involved in memory write operation??

asked 2 days ago in CO & Architecture by Sarthak Mittal (7 points) | 7 views

0 votes

1 answer

24

Addressing mode
Solution please

answered 3 days ago in CO & Architecture by shaz (171 points) | 51 views

0 votes

0 answers

25

METest_COA
Consider professor vamshi writes a program given below and run on a system which has 2way set associative 16KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy is used. and the base address of the array is $0x0$ and ... new block is accessed which causes a cache miss. Total misses=$1023+128=1151$ Please let me know If I went somewhere wrong.

asked 3 days ago in CO & Architecture by Ayush Upadhyaya Boss (18.9k points) | 31 views

0 votes

0 answers

26

#madeeasy test series

asked 3 days ago in CO & Architecture by Soumya Tiwari Active (2k points) | 13 views

+2 votes

1 answer

27

Made easy
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are 50 cycles. The hit time of L2 cache is 10 cycles. The hit time of the L1 cache is 5 cycles. If there are 1.25 memory references per instruction, then the average stall cycles per instruction is ________.

answered 3 days ago in CO & Architecture by Debargha Bhattacharj (39 points) | 96 views

0 votes

0 answers

28

https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial

asked 3 days ago in CO & Architecture by sushmita Boss (15.3k points) | 38 views

0 votes

0 answers

29

General doubt.
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?

asked 3 days ago in CO & Architecture by sushmita Boss (15.3k points) | 14 views

0 votes

0 answers

30

conceptual doubt
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula- AMAT= H1*T1+(1-H1(T1+T2)) T1- cache access time/word T2= memory access time/word T2 ... in some cases we just take word access time of main memory. also please tell me what should be T2 in case of simultaneous organization?

asked 3 days ago in CO & Architecture by sushmita Boss (15.3k points) | 19 views

+1 vote

2 answers

31

made easy

answered 3 days ago in CO & Architecture by Debargha Bhattacharj (39 points) | 150 views

0 votes

0 answers

32

Cache indexing
What is the meaning of cache indexing?

asked 3 days ago in CO & Architecture by Ajit J (313 points) | 26 views

0 votes

5 answers

33

DMA
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. What percentage of time is the CPU in busy mode (approximately)?

answered 4 days ago in CO & Architecture by amytrkpatel (51 points) | 852 views

0 votes

0 answers

34

ME Test Series

asked 4 days ago in CO & Architecture by Shadan Karim (353 points) | 16 views

0 votes

1 answer

35

made eassy test
consider a chache with 32 blocks and each block of size 32 byte. The byte address 1216 of main memory will mapped which line of cache

answered 4 days ago in CO & Architecture by twin_123 (139 points) | 32 views

+1 vote

1 answer

36

UGCNET-Jan2017-III-6
In 8085, which of the following performs : load register pair immediate operation ? (1) LDAX rp (2) LHLD addr (3) LXI rp, data (4) INX rp

answered 4 days ago in CO & Architecture by Adnan Ashraf (35 points) | 148 views

0 votes

0 answers

37

Madeeasy-Test-series
consider a RISC processor with an ideal CPI ,where 25% of total instructions are Load and Store instruction.Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles .if cache miss rate is 2% , then the effective CPI for the system with the cache is __.{upto 2 decimal}.

asked 4 days ago in CO & Architecture by Prateek Raghuvanshi Loyal (8k points) | 69 views

0 votes

0 answers

38

speedup
An application program is executed on a nine-computer cluster. A benchmark program took time T on this cluster. Further, it was found that 25% of T was time in which the application was running simultaneously on all nine computers.The remaining time, the ... the percentage of code that has been parallelized (programmed or compiled so as to use the cluster mode) in the preceding program

asked 4 days ago in CO & Architecture by aambazinga Active (2.1k points) | 23 views

0 votes

2 answers

39

GATEBOOK-2019-COA1-16
Consider a two words instruction $\text{CPY LOC1 LOC2 DATA}$ which copies the content of a file $\text{DATA}$ from one location in memory, $\text{LOC1}$ to other location in memory, $\text{LOC2}$ on a $32$-bit $80$ GHz machine. The processing module is made ... from $\text{LOC1 to LOC2}$ the amount of time needed (in ns) to execute the instruction is: $370$ $385$ $332$ $392$

answered 4 days ago in CO & Architecture by Ayush Upadhyaya Boss (18.9k points) | 52 views

0 votes

1 answer

40

ACE TEST SERIES QUESTION

answered 4 days ago in CO & Architecture by Devwritt Active (3.9k points) | 25 views

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