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Recent questions and answers in CO and Architecture

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1

DMA
The below question is from Made Easy Test series The diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data transfer using DMA(Consider only data transfer, not command or status transfer) 1 2 3 0 Here answer ... My Doubt: In DMA their is direct data transfer from i/o to memory so system bus is accessed only once. Is this correct?

Shubham Sharma 2 answered in CO and Architecture 1 day ago

by Shubham Sharma 2

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1 answer

2

igate test series
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline ... wrong. approch totel 200 in which (100 add having 1 cc) +(25*5-1) +(75*(3-1))=354

lalitver10 answered in CO and Architecture 1 day ago

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48 votes

9 answers

3

GATE CSE 2014 Set 1 | Question: 43
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this $6$-stage pipeline, the speedup achieved with respect to non-pipelined execution if $25$% of the instructions incur $2$ pipeline stall cycles is ____________

svas7246 answered in CO and Architecture 6 days ago

14.2k views

1 vote

1 answer

4

Test Series
Question : Consider a Device which operates with 20 MBPS operating speed.The device is operating on Programmed control mode of I/O and it has to transfer data of 20 B from it the data is transferred byte wise .Size of status register is 2 Bytes.total time needed to perform the data transfer is --------(microseconds)

Pranavpurkar answered in CO and Architecture Sep 22

by Pranavpurkar

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1 answer

5

DMA cycle stealing
Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is ready or prepared. Percentage of CPU blocked due to DMA?

Amitap123 answered in CO and Architecture Sep 21

868 views

49 votes

10 answers

6

GATE CSE 2004 | Question: 68
A hard disk with a transfer rate of $10$ Mbytes/second is constantly transferring data to memory using DMA. The processor runs at $600$ MHz, and takes $300$ and $900$ ... percentage of processor time consumed for the transfer operation? $5.0 \%$ $1.0\%$ $0.5\%$ $0.1\%$

Sumit Singh Dhami answered in CO and Architecture Sep 20

by Sumit Singh Dhami

21.0k views

1 vote

2 answers

7

University Assignment
Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. ... For how long would the device tie up the bus when transferring a block of 128 bytes? b)Repeat the calculation for cycle-stealing mode

afroze answered in CO and Architecture Sep 20

by afroze

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1 answer

8

ISI 2021 | PCB CS | Question: 7.b
Consider a $4$-way set associative cache mapping, in which the cache blocks are grouped into sets and each set has $4$ blocks. There are $16$ cache blocks in total. The following memory block requests arrive in order when ... . Show the cache configuration (along with intermediate configurations) on meeting the above memory requirements. What is the hit ratio?

Vishnu__ answered in CO and Architecture Sep 16

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1 answer

9

Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So: a) How many multiplexer is needed? b) What type of multiplexer is required i.e size of multiplexer? c) Describe decoder used to select address of memory unit

Vishnu__ answered in CO and Architecture Sep 16

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1 answer

10

#Exam
Pipe line consists of 5 stages , add instruction takes 2 cycles in EX stage, mul instruction takes 3 cycles in EX stage .. If we don't use buffer in between stages(no store and forward) , what is the time taken to execute two instruction add,mul???

lalitver10 answered in CO and Architecture Sep 14

52 views

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1 answer

11

prepladder question bank
How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable.

RamaSivaSubrahmanyam answered in CO and Architecture Sep 12

by RamaSivaSubrahmanyam

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0 answers

12

#pipelining self-doubt
In pipielining add instruction takes 2 cycles in execution stage and mul instruction takes 4 clock cycles in the execution stage and in the remaining stages each instruction takes 1 cycle ... Now if we execute both instruction parlelly in pipelining , we get 2 stalls .. Now the question is , how do we treat those stalls? That means are they hazards or simply stalls??

RamaSivaSubrahmanyam asked in CO and Architecture Sep 12

by RamaSivaSubrahmanyam

35 views

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0 answers

13

control signal
What will be the control signal for executing the 32-bit instruction PC=PC+4? Explain each of the steps in single sentence.

Abhi patil asked in CO and Architecture Sep 12

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0 answers

14

Applied Gate Test Series

lalitver10 asked in CO and Architecture Sep 10

68 views

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1 answer

15

Cache Coherence
A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C0$ writes to $A$ and afterwards $C1$ reads from $A$. This happens for 1000 times. Find number of times system bus is used by the program..

Ratul Chatterjee answered in CO and Architecture Sep 10

by Ratul Chatterjee

566 views

–1 vote

1 answer

16

Carl Hamacher Cache Memory
What should be correct answer to this question? In solution it's option A in Carl hamacher text book it's B ? I am confused please help

Ratul Chatterjee answered in CO and Architecture Sep 10

by Ratul Chatterjee

609 views

0 votes

1 answer

17

UNDEFINED
in a 5 stage pipeline processor a program consist of 50 instruction suppose there are 20% instruction require 1 extra stall cycle what is the cpi from this execution ?

Ratul Chatterjee answered in CO and Architecture Sep 8

by Ratul Chatterjee

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1 answer

18

[email protected] 2022

Arun Madhav answered in CO and Architecture Sep 7

72 views

2 votes

2 answers

19

Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40

jeetblahiri answered in CO and Architecture Sep 7

1.6k views

2 votes

3 answers

20

GATE CSE 1987 | Question: 2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.

Abhrajyoti00 answered in CO and Architecture Sep 7

by Abhrajyoti00

1.2k views

1 vote

4 answers

21

Madeeasy- Types of Dependencies
Please clarify along with the names.

Abhrajyoti00 answered in CO and Architecture Sep 7

by Abhrajyoti00

696 views

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1 answer

22

Computer Org and A1
Total: n instruction Total conditional statement probability :p and True condition probability:q i)Branch is known at end of t satge Effective CPI = [npq*(t+1) + (n-npq)*1)]/n OR ii) Penality is t stall cycle same i.e Effective CPI = [npq*(t+1) + (n-npq)*1)]/n OR iii) Effective CPI= 1+ stall freq*stall penality =1+pq*t am i correct???

Ratul Chatterjee answered in CO and Architecture Sep 7

by Ratul Chatterjee

128 views

1 vote

1 answer

23

Ratul Chatterjee answered in CO and Architecture Sep 7

by Ratul Chatterjee

445 views

0 votes

1 answer

24

Ratul Chatterjee answered in CO and Architecture Sep 7

by Ratul Chatterjee

164 views

0 votes

1 answer

25

Self doubt
If the time taken by a task to get completed is same in the pipeline and non pipeline circuits, then how the time taken to complete the task in non pipeline = k* time taken to complete the task in pipeline where k is no. of segments in the pipeline?

Ratul Chatterjee answered in CO and Architecture Sep 7

by Ratul Chatterjee

199 views

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1 answer

26

Avoiding pipeline Hazards
Please Confirm.

Ratul Chatterjee answered in CO and Architecture Sep 7

by Ratul Chatterjee

341 views

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1 answer

27

#architecture
What is meant by 32 -bit and 64- bit architecture means... Does it represent wordsize or something else???

kanakjyoti answered in CO and Architecture Sep 6

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1 answer

28

COA
Please Explain : “ sp content is incremented for stack going downward method and decrement for stack going upward method”

felix59 answered in CO and Architecture Sep 5

48 views

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1 answer

29

Test Series
A two-word instruction "JMP 65" is located from the address 200010. What is the effective address computed if the instruction follows relative addressing mode? My answer is 2065, Why should it be 2067

Ratul Chatterjee answered in CO and Architecture Sep 5

by Ratul Chatterjee

156 views

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1 answer

30

Ratul Chatterjee answered in CO and Architecture Sep 5

by Ratul Chatterjee

76 views

1 vote

1 answer

31

NIELIT STA 2021
The addressing mode / s, which uses the PC instead of a general-purpose register is: Indexed with offset Relative Direct Both Indexed with offset and direct

Ratul Chatterjee answered in CO and Architecture Sep 5

by Ratul Chatterjee

120 views

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0 answers

32

Interrupts
If Some device wants to Transfer some bytes into memory ?? .. By using which signal the Device will contact the CPU?? READY[I am ready to transfer] Or INTR

RamaSivaSubrahmanyam asked in CO and Architecture Sep 4

by RamaSivaSubrahmanyam

23 views

0 votes

0 answers

33

Computer Organization and Architecture
Please clarify the fourth option only. My doubt: if the same word in requires repeatedly, then for the first the word will be miss and there after it is continuously in use how it can be miss.

GateOverflow04 asked in CO and Architecture Sep 3

by GateOverflow04

33 views

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0 answers

34

Computer Organization and Architecture
While calculating the average read time , why 0.9*10 + 0.1*(10+110) is not used. .i.e. why cache time is not added in miss frequency.

GateOverflow04 asked in CO and Architecture Sep 3

by GateOverflow04

31 views

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1 answer

35

Gate [email protected] Test Series 2022
Ans is 2168 Please help someone

Kabir5454 answered in CO and Architecture Sep 3

61 views

0 votes

1 answer

36

Accesing time
Could you please differentiate below . Memory access time .hit time . search time ?? Arey yar some one answer this.. why so dumb

Vishnu__ answered in CO and Architecture Sep 3

42 views

0 votes

1 answer

37

ISI 2021 | PCB CS | Question: 7.a
Consider the single precision (i.e., $32$-bit) floating point representation of numbers in the normalized form where $8$ bits are used for the exponent with the bias of $127.$ What is the binary representation of $-10.4$ in the above form? The steps followed to arrive at the ... between $2^{-18}$ and $2^{-17}$ (i.e., excluding $2^{-18}$ and $\left.2^{-17}\right)?$

Vishnu__ answered in CO and Architecture Sep 3

30 views

2 votes

3 answers

38

GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput? $\text{DMA}$ based $\text{I/O}$ transfer Interrupt driven $\text{I/O}$ transfer Polling based $\text{I/O}$ transfer Programmed $\text{I/O}$ transfer

Abhrajyoti00 answered in CO and Architecture Sep 2

by Abhrajyoti00

1.2k views

0 votes

1 answer

39

Microprogrammed control unit
Can anyone explain microprogrammed control unit? Also what is horizontal microcode and vertical microcode?

Ratul Chatterjee answered in CO and Architecture Sep 2

by Ratul Chatterjee

182 views

0 votes

1 answer

40

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

Ratul Chatterjee answered in CO and Architecture Sep 2

by Ratul Chatterjee

154 views

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