# Recent questions and answers in CO and Architecture

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The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF
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A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
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Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
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In IEEE $754$ single floating point format, how many numbers can be represented in the interval [10, 16)? A. $2^{21}$ B. $3 * 2^{21}$ C. $5 * 2^{21}$ D. $2^{22}$
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Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence? Instruction fetch Operand fetch Conditional branch Initiation of interrupt service
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Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $\text{25%}$ less time but incurs $\text{20%}$ more CPI (clock cycles per instruction) as compared to the program ... $P_1$. If the clock frequency of $P_1$ is $\text{1GHZ}$, then the clock frequency of $P_2$ (in GHz) is ______.
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How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
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Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
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A certain computer system was designed with cache memory of size $1$ Kbytes and main memory size of $256$ Kbytes. The cache implementation was fully associative cache with $4$ bytes per block. The CPU memory data path was $16$ ... Answer the following questions: What is the hit ratio? Suggest a change in the program size of model to improve the hit ratio significantly.
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An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
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Shouldn't the number of dependencies be 5 (2 because of R1 & 3 because of R2).
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ADD R1 , R2, R2;  ADD R3, R2, R1; SUB R4, R1 , R5; ADD R3, R3, R4; FIND THE NUMBER OF READ AFTER WRITE(RAW) DEPENDENCIES IN THE ABOVE CODE.
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Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 &ndash; R6$ I3: ADD $R1 \leftarrow R2 + R3$ I4: STORE ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4
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what is 10x and 5x ?
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A byte addressable computer has a memory capacity of $2$^{m}$KB$ ($k$ bytes) and can perform $2$^{n}$operations. An instruction involving$3$operands and one operator needs maximum of:$3m$bits$3m + n$bits$m + n$bits none of the above 53 votes 12 answers 20 Consider a disk drive with the following specifications:$16$surfaces,$512$tracks/surface,$512$sectors/track,$1$KB/sector, rotation speed$3000$rpm. The disk is operated in cycle stealing mode whereby whenever one$4$byte word is ready it is sent to memory; similarly, ... is$40$nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:$10254050$5 votes 4 answers 21 How many total bits are required for a direct-mapped cache with$128$KB of data and$1$word block size, assuming a$32$-bit address and$1$word size of$4$bytes?$2$Mbits$1.7$Mbits$2.5$Mbits$1.5$Mbits 0 votes 1 answer 22 Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline. 0 votes 2 answers 23 A non-pipeline system takes$50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of$10$ns. Determine approximately the speedup ratio of the pipeline for$500$tasks.$64.955.75.5$0 votes 1 answer 24 Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1) 3 votes 1 answer 25 A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places) 32 votes 9 answers 26 A certain processor deploys a single-level cache. The cache block size is$8$words and the word size is$4$bytes. The memory system uses a$60$-MHz clock. To service a cache miss, the memory controller first takes$1$cycle to accept the starting ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$bytes/sec 6 votes 5 answers 27 A direct mapped cache memory of$1$MB has a block size of$256$bytes. The cache has an access time of$3$ns and a hit rate of$94 \%$. During a cache miss, it takes$2$0 ns to bring the first word of a block from the main memory, while each subsequent word takes$5$ns. The word size is$64$bits. The average memory access time in ns (round off to$1$decimal place) is______. 0 votes 3 answers 28 The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above 1 vote 5 answers 29 A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these. 50 votes 4 answers 30 In a two-level cache system, the access times of$L_1$and$L_2$caches are$1$and$8$clock cycles, respectively. The miss penalty from the$L_2$cache to main memory is$18$clock cycles. The miss rate of$L_1$cache is twice that of$L_2$. The average memory access time (AMAT) of ... and$L_2$respectively are$0.111$and$0.0560.056$and$0.1110.0892$and$0.17840.1784$and$0.0892$3 votes 2 answers 31 Consider the following instruction sequence where registers$\text{R1}, \text{R2}$and$\text{R3}$are general purpose and$\text{MEMORY[X]}$denotes the content at the memory location$\text{X}.$... decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location$3010$is ____________ 30 votes 4 answers 32 The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic 77 votes 10 answers 33 Consider a two-level cache hierarchy with$L1$and$L2$caches. An application incurs$1.4$memory accesses per instruction on average. For this application, the miss rate of$L1$cache is$0.1$; the$L2$cache experiences, on average,$7$misses per$1000$instructions. The miss rate of$L2$expressed correct to two decimal places is ________. 65 votes 8 answers 34 A computer system has an$L1$cache, an$L2$cache, and a main memory unit connected as shown below. The block size in$L1$cache is$4$words. The block size in$L2$cache is$16$words. The memory access times are$2$nanoseconds,$20$... from$L2$cache to$L1$cache. What is the time taken for this transfer?$2$nanoseconds$20$nanoseconds$22$nanoseconds$88$nanoseconds 79 votes 8 answers 35 Consider a three word machine instruction$\text{ADD} A[R_0], @B$The first operand (destination)$ A[R_0] $uses indexed addressing mode with$R_0$as the index register. The second operand (source)$ @B $uses indirect addressing mode.$A$and$B$are memory ... the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is:$3456$4 votes 3 answers 36 Consider a set-associative cache of size$\text{2KB (1KB} =2^{10}$bytes$\text{)}$with cache block size of$64$bytes. Assume that the cache is byte-addressable and a$32$-bit address is used for accessing the cache. If the width of the tag field is$22\$ bits, the associativity of the cache is _________
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Suppose that an unpipelined processor has a cycle time of 25ns, and that it's data path is made up of modules with latencies of 2,3,4,7,3,2 and 4ns(in that order).In pipelining this processor ,it is not possible to rearrange the order of the modules(for examples, putting the register ... 1,what is the latency of the pipeline? (a). no latency (b). 35 ns latency (c). 40 ns latency (d). 56 ns latency