Suppose that an unpipelined processor has a cycle time of 25ns, and that it's data path is made up of modules with latencies of 2,3,4,7,3,2 and 4ns(in that order).In pipelining this processor ,it is not possible to rearrange the order of the modules(for examples, putting the register ... 1,what is the latency of the pipeline? (a). no latency (b). 35 ns latency (c). 40 ns latency (d). 56 ns latency
answered
Mar 27
in CO and Architecture
sauravgahlawat
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