# Recent questions and answers in CO and Architecture

1
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2 \hspace{0.1cm} nanoseconds$ ... this transfer? $2 \hspace{0.1cm} nanoseconds$ $20 \hspace{0.1cm} nanoseconds$ $22 \hspace{0.1cm}nanoseconds$ $88 \hspace{0.1cm} nanoseconds$
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In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller ... smaller block size implies a larger cache tag and hence lower cache hit time A smaller block size incurs a lower cache miss penalty
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Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
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Suppose that an unpipelined processor has a cycle time of 25ns, and that it's data path is made up of modules with latencies of 2,3,4,7,3,2 and 4ns(in that order).In pipelining this processor ,it is not possible to rearrange the order of the modules(for examples, putting the register ... 1,what is the latency of the pipeline? (a). no latency (b). 35 ns latency (c). 40 ns latency (d). 56 ns latency
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Consider the following expression and identify minimum number of registers required to implement the following expression : (a-b)+(e+(c-d))/f Can anyone please give the theory or notes of prerequisites -, how to solve these questions. The solution of the above problem is :- ... performed by adding R1 to the R2 and result is stored back into R1 since R1=R1+R2. Number of registers used is only 3.
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A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction execution in each of the ... in 4 clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.
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Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is 3.2 3.0 2.2 2.0
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Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) respectively. A pipelined ... . The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________ .
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A particular parallel program computation requires $100$ sec when executed on a single processor, if $40$% of this computation is inherently sequential (i.e. will not benefit from additional processors), then theoretically best possible elapsed times of this program running with $2$ and $4$ processors, respectively, ... $30$ $sec$ and $15$ $sec$ $50$ $sec$ and $25$ $sec$ $70$ $sec$ and $55$ $sec$
1 vote
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The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
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A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and $Y$ represent the number ... control data register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(
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A micro programmed control unit Is faster than a hardwired unit Facilitates easy implementation of a new instruction Is useful when small programs are to be run All of the above
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Micro program is the name of source program in micro computers the set of instructions indicating the primitive operations in a system primitive form of macros used in assembly language programming program of very small size
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Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
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Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup}$ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
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In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
1 vote
17
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
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Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
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Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ processor. If $0.5 \%$ processor cycles are used for $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
1 vote
20
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
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Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
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The principle of locality justifies the use of: Interrupts DMA Polling Cache Memory
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What is cache memory? What is rationale of using cache memory?
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Assume that the hit time of a two-way set-associative first-level data cache is 1.1 times faster than a four-way set-associative cache of the same size. The miss rate falls from 0.049 to 0.044 for an 8 KB data cache, Assume a hit is 1 clock cycle and that ... to the L2 cache for the two-way set-associative cache, and that the L2 cache does not miss. Which has the faster average memory access time?
1 vote
25
Assume that the control memory is 24 bits wide. The control portion of the microinstruction format is divided into two fields.A micro-operation field of 11 bits specifies the micro-operations to be performed. An address selection field specifies a condition, based on the flags, ... selection field? b. How many bits are in the address field? c. What is the maximum size of the control memory?
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The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$
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A processor can support a maximum memory of $4GB$, where the memory is word-addressable (a word consists of two bytes). The size of address bus of the processor is at least _________bits.
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The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$ and Writeback $(WB)$, The $IF$, $ID$, $OF$ and $WB$ stages take $1$ ... there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____.
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A processor has $16$ integer registers $(R0, R1, \ldots , R15)$ and $64$ floating point registers $(F0, F1, \ldots , F63).$ It uses a $2- byte$ instruction format. There are four categories of instructions: $Type-1, Type-2, Type-3,$ and $Type-4.$ $Type-1$ ... $Type-4$ category consists of $N$ instructions, each with a floating point register operand $(1F).$ The maximum value of $N$ is _____
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A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec
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The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF
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A system which has lot of crashes, data should be written to the disk using A. Write-through B. Wtite-back C. Both
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A micro program control unit is required to generate a total of 25 control signals. Assume that during any micro instruction, at most two control signals are active. The number of bits required in the control word to generate the required control signals ... In this question I am asking about horizontal microprogramming) previous year gate question link:https://gateoverflow.in/2754/gate1996-2-25
34
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... are for instruction fetch and $40$% are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________
1 vote
35
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
36
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$
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A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
Which of the following statements with respect to multiprocessor system are true? Multiprocessor system is controlled by one operating system In Multiprocessor system, multiple computers are connected by the means of communication lines Multiprocessor system is classified as multiple instruction stream and multiple data stream ... $(b)$ only $(a)$ and $(c)$ only $(b)$ and $(c)$ only
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct answer from the ... are false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true