Recent questions and answers in CO and Architecture

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1

NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.

asked 1 day ago in CO and Architecture by Lakshman Patel RJIT Veteran (61.3k points) | 7 views

+7 votes

6 answers

2

ISRO2014-17
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 $\times$ 6 array, where each chip is 8K $\times$ 4 bits ? 13 15 16 17

answered 3 days ago in CO and Architecture by habedo007 Active (3k points) | 5.5k views

+2 votes

1 answer

3

doubt in coa
is it 5 or 4 ..?? some places i am finding it as 4 (number of cycles) and in some places it is given as 5(number of slots)..please confirm

answered 3 days ago in CO and Architecture by tech_beardo (229 points) | 55 views

0 votes

1 answer

4

UGCNET-Dec2004-II: 47
The processing speeds of pipeline segments are usually : Equal. Unequal. Greater. None of these.

answered 3 days ago in CO and Architecture by Kumar1712 (11 points) | 10 views

+68 votes

10 answers

5

GATE2016-2-30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement the computation $F(G(X_{i}))$ for $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 8.9k views

+49 votes

6 answers

6

GATE2016-1-32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 9.7k views

+27 votes

5 answers

7

GATE2016-1-31
The size of the data count register of a $\text{DMA}$ controller is $16 \text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________-.

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 5.9k views

+21 votes

9 answers

8

GATE2017-2-53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is _______

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 3.7k views

+59 votes

9 answers

9

GATE2017-1-25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 8.8k views

+35 votes

5 answers

10

GATE2018-51
A processor has $16$ integer registers $(R0, R1, \ldots , R15)$ and $64$ floating point registers $(F0, F1, \ldots , F63).$ It uses a $2- byte$ instruction format. There are four categories of instructions: $Type-1, Type-2, Type-3,$ and $Type-4.$ ... $Type-4$ category consists of $N$ instructions, each with a floating point register operand $(1F).$ The maximum value of $N$ is _____

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 8.2k views

+1 vote

4 answers

11

gate 2018 cs
physical address space of the omputer system is 2^p bytes , word size is 2^w bytes , cache memory has 2^n bytes and cache block size is 2^m words,k-way set associative is used for mapping from main memory to cache memory .the size of the tag bit is???

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 1.5k views

+11 votes

6 answers

12

GATE2018-5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 3.5k views

+17 votes

3 answers

13

GATE2018-23
A $32$-$bit$ wide main memory unit with a capacity of $1\;GB$ is built using $256$ $M \times 4-bit$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The time taken to perform one refresh ... milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is_____.

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 6.6k views

+17 votes

8 answers

14

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 4k views

+1 vote

2 answers

15

UGCNET-June-2019-II-14
The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents of flags and counters registers and counters flags and registers flags, registers and counters

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 293 views

+21 votes

4 answers

16

GATE2009-8, UGCNET-June2012-III-58
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 5.6k views

+4 votes

5 answers

17

UGCNET-June2016-III-5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 1.7k views

0 votes

2 answers

18

UGCNET-June2016-III-4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register

answered Mar 24 in CO and Architecture by topper98 Junior (589 points) | 1.5k views

+1 vote

1 answer

19

cache
In a particular system it is observed that, the cache performance get improved as a result of increasing the block size of the cache. The primary reason behing this is: 1. Program exhibits temporal locality 2. Programs have small working set 3. Read ... rather than write operation 4. Program exhibits spatial locality What would the answer to this Question ? asked in NIELIT assistant paper..

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 287 views

0 votes

2 answers

20

Determine Access time of system
If Cache access time is 10 ns . main memory access time is 150 ns. Cache hit rate is 99%. Determine effective access time of system.

answered Mar 23 in CO and Architecture by smsubham Boss (16k points) | 88 views

+3 votes

2 answers

21

RAM Chip
A RAM chip has 7 address line , 8 data lines and 2 chips select lines. Then the number of memory locations is ... a. 2^12 b.2^10 c.2^19 d.2^13 Plz describe with a proper diagram and significance of each lines.

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 1.1k views

+2 votes

2 answers

22

NIELIT Scientist-B Dec 2017_1
INCA (Increase register A by 1) ia an example of which of the following addressing mode ? (A) Immediate addressing (B) Indirect addressing (C) Implied addressing (D) Relative addressing

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 433 views

+1 vote

2 answers

23

NIELIT Scientist-B Dec 2017_33
Consider anon-pipelined machine with 6 stages; the length of each stage are 20ns, 10ns, 30ns, 25ns, 40ns, and 15ns respectively. Suppose for implementing the pipelining the machine adds 5ns of overhead to each stage for clock skew and set up. What is the speed up factor of thr pipelining system (ignoring any hazard imapact) ? (A) 7 (B) 14 (C) 3.11 (D) 6.22

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 332 views

0 votes

1 answer

24

MadeEasy Full Length Test 2018: CO & Architecture - Cache Memory
Consider the following cache A and B .let the average access times in cache A and B is $t_A$ and $t_B$ respectively.the value of $t_A+t_B$ _(in ns) Answer is given as 30.18 ns I am getting 31.2 ns .Please verify it .

answered Mar 23 in CO and Architecture by smsubham Boss (16k points) | 197 views

+10 votes

5 answers

25

ISRO2015-77
In $X=(M+N \times O)/(P \times Q)$, how many one-address instructions are required to evaluate it? 4 6 8 10

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 3.2k views

+1 vote

2 answers

26

A non-pipeline system 50ns to process a task....
A non-pipeline system 50ns to process a task. The same task can be processed in a 6 segment pipeline with a clock cycle of 10ns. Determine the speed of ratio of pipeline system for 100 tasks . What is the maximum speed up that can be achieved?

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 1.3k views

0 votes

1 answer

27

MADEEASY- CO - SET Associative mapping
Assume a new cache design is proposed by a student. But he later discovered design has too many conflict misses and to resolve this issue he increases the associativity in the design. Which of the following implication will occur in the ... bit increases C. No implications in the design what does INDEX bits refers to in set associative and associative mapping?

answered Mar 23 in CO and Architecture by smsubham Boss (16k points) | 138 views

0 votes

2 answers

28

MadeEasy Test Series: CO & Architecture - Cache Memory

answered Mar 23 in CO and Architecture by smsubham Boss (16k points) | 89 views

0 votes

2 answers

29

Nielit 2017
Which memory is difficult to interface with processor? And why 1. Static memory 2.Dynamic memory 3.ROM 3.NOT Please explain it

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 593 views

0 votes

2 answers

30

Number of bits - Instruction format
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 ... and an address part. How many bits are there in the operation code, the register code part, and the address part respectively?

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 312 views

+26 votes

6 answers

31

GATE2001-1.10, UGCNET-Dec2012-III-36
Suppose a processor does not have any stack pointer registers, which of the following statements is true? It cannot have subroutine call instruction It cannot have nested subroutines call Interrupts are not possible All subroutine calls and interrupts are possible

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 4.9k views

+2 votes

2 answers

32

How many address lines are needed to address each memory locations in a 2048 x 4 memory chip

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 1.5k views

+1 vote

3 answers

33

ugc net july 2018 -100
In 8085 microprocessor, what is the output of following program ? LDA 8000H MVI B, 30H ADD B STA 8001H (1) Read a number from input port and store it in memory (2) Read a number from input device with address 8000H and store it in memory at location 8001H ( ... explanation .. i think ans should be 3 but ans is given by ugc is 4 please help? i want to Challenge of Answer Key.

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 737 views

0 votes

3 answers

34

ugc net 2018 july -91
CMOS is a Computer Chip on motherboard which is: RAM ROM EPROM Auxillary memory

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 870 views

+11 votes

5 answers

35

ISRO2014-1
Consider a 33MHz cpu based system. What is the number of wait states required if it is interfaced with a 60ns memory? Assume a maximum of 10ns delay for additional circuitry like buffering and decoding. 0 1 2 3

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 6.1k views

+9 votes

5 answers

36

ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time will the processor be slowed down due to DMA activity? $9.6$ms $4.8$ms $2.4$ms $1.2$ms

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 3.8k views

+8 votes

7 answers

37

ISRO-2013-15
A pipeline $P$ operating at $400$ MHz has a speedup factor of $6$ and operating at $70$% efficiency. How many stages are there in the pipeline? $5$ $6$ $8$ $9$

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 4.3k views

+6 votes

5 answers

38

ISRO-2013-16
How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory. $5.27$ $2.00$ $4.16$ $6.09$

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 5.2k views

+4 votes

5 answers

39

ISRO-2013-35
How many number of times the instruction sequence below will loop before coming out of the loop? MOV AL, 00H A1: INC AL JNZ A1 1 255 256 Will not come out of the loop.

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 2.4k views

+26 votes

6 answers

40

GATE2007-IT-6, ISRO2011-25
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$

answered Mar 23 in CO and Architecture by topper98 Junior (589 points) | 4.9k views

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