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Recent questions and answers in CO and Architecture

30 votes
8 answers
1
GATE2006-09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
answered 1 day ago in CO and Architecture SPeedSter 6.4k views
2 votes
3 answers
2
Bit Map
A bit-map can be used to keep track of which blocks are free in a file-system’s partition on disk. Assuming, 1 KB block size and a disk size of 40 GB, what is the size of the bit map?
A bit-map can be used to keep track of which blocks are free in a file-system’s partition on disk. Assuming, 1 KB block size and a disk size of 40 GB, what is the size of the bit map?
answered 5 days ago in CO and Architecture Himanshu Kumar Gupta 817 views
5 votes
2 answers
4
Gateoverflow Computer architecture 2 exam question
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit ... per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit time in L1 cache is 10 cycles ... number of stall cycles per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.
answered Sep 19 in CO and Architecture shivani.sinha07 317 views
12 votes
7 answers
5
GATE2018-5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
answered Sep 16 in CO and Architecture Sanandan 4.6k views
16 votes
2 answers
6
GATE1995-1.6
The principle of locality justifies the use of: Interrupts DMA Polling Cache Memory
The principle of locality justifies the use of: Interrupts DMA Polling Cache Memory
answered Sep 15 in CO and Architecture Sanandan 3k views
0 votes
1 answer
7
MadeEasy Test Series: CO & Architecture - Dma
A hard disk with a transfer rate of 1 KBps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The processor runs at 400 kHz clock frequency. The DMA controller requires ... time as 0.9375 sec and percentage time CPU gets blocked = transfer time/preparation time (IN case of cycle stealing)
A hard disk with a transfer rate of 1 KBps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The processor runs at 400 kHz clock frequency. The DMA controller requires 10 cycles for initialization ... and preparation time as 0.9375 sec and percentage time CPU gets blocked = transfer time/preparation time (IN case of cycle stealing)
answered Sep 13 in CO and Architecture Sanandan 451 views
48 votes
5 answers
9
GATE2004-IT-51
The storage area of a disk has the innermost diameter of $10$ cm and outermost diameter of $20$ cm. The maximum storage density of the disk is $1400$ bits/cm. The disk rotates at a speed of $4200$ RPM. The main memory of a computer has $64$-bit word length and ... transfer from the disk, the percentage of memory cycles stolen for transferring one word is $0.5 \%$ $1 \%$ $5\%$ $10\%$
The storage area of a disk has the innermost diameter of $10$ cm and outermost diameter of $20$ cm. The maximum storage density of the disk is $1400$ bits/cm. The disk rotates at a speed of $4200$ RPM. The main memory of a computer has $64$-bit word length and $1$µs ... data transfer from the disk, the percentage of memory cycles stolen for transferring one word is $0.5 \%$ $1 \%$ $5\%$ $10\%$
answered Sep 12 in CO and Architecture gatecse 7.9k views
45 votes
9 answers
10
GATE2005-70
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$
answered Sep 12 in CO and Architecture gatecse 17.8k views
4 votes
4 answers
11
GATE 2020 CSE | Question: 21
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while ... word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while each subsequent word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
answered Sep 12 in CO and Architecture bhupendrakumar 3.6k views
0 votes
1 answer
12
cache memory
Consider a two level memory hierarchy, L1 (cache) has an accessing time of 5 ns and main memory has an accessing time of 100 ns. Writing or updating contents takes 20 ns and 200 ns for L1 and main memory respectively. Assume L1 gives misses 20% ... 60% of the instructions are read only instructions. What is the average access time for system (in ns) if it uses WRITETHROUGH technique?
Consider a two level memory hierarchy, L1 (cache) has an accessing time of 5 ns and main memory has an accessing time of 100 ns. Writing or updating contents takes 20 ns and 200 ns for L1 and main memory respectively. Assume L1 gives misses 20% of the time with 60% of the instructions are read only instructions. What is the average access time for system (in ns) if it uses WRITETHROUGH technique?
answered Sep 10 in CO and Architecture arun yadav 307 views
15 votes
2 answers
13
GATE1999-17
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. The meanings of the instructions are shown by comments (starting with ;) after the instructions. X: CMP ... contain the values n, 0, and 0 respectively. What is the final value of $R3$ when control reaches $Z$?
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. The meanings of the instructions are shown by comments (starting with ;) after the instructions. X: CMP R1, 0; ... $R3$ when control reaches $Z$?
answered Sep 10 in CO and Architecture Nithish 2.3k views
0 votes
1 answer
14
Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?
answered Sep 9 in CO and Architecture Himanshu Kumar Gupta 111 views
77 votes
6 answers
15
GATE2014-1-44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed through a cache ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed through a cache of ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$
answered Sep 9 in CO and Architecture sujithrkumar 10k views
1 vote
1 answer
16
MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache is ... four words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)
answered Sep 9 in CO and Architecture Himanshu Kumar Gupta 232 views
0 votes
3 answers
18
ME TEST SERIES
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probability of an instruction being a branch instruction then the value of p such that speed up is atleast 3 is ________. (Upto 2 decimal places)
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probability of an instruction being a branch instruction then the value of p such that speed up is atleast 3 is ________. (Upto 2 decimal places)
answered Sep 8 in CO and Architecture Sanandan 497 views
1 vote
4 answers
19
Ace Test Series: CO & Architecture - SpeedUp In Pipeline
Consider a non­pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is
Consider a non­pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is
answered Sep 8 in CO and Architecture Sanandan 436 views
0 votes
1 answer
20
stage delays doubt in pipelining
if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last stage. each register delay is 1ns. How the time taken by a NON-PIPELINED implementation is calculated for n no. of instructions? and what is the speed up here?
if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last stage. each register delay is 1ns. How the time taken by a NON-PIPELINED implementation is calculated for n no. of instructions? and what is the speed up here?
answered Sep 8 in CO and Architecture Sanandan 352 views
0 votes
2 answers
21
MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
answered Sep 8 in CO and Architecture Sanandan 364 views
2 votes
3 answers
23
Deadlock detection
Which of the following is true? S1: If there is a cycle in RAG then there will be a deadlock S2: If there is a cycle in RAG where all the resources are havinng single instance then there will be a deadlock S3: Unsafe state results in deadlock S4: Deadlock states is subset of unsafe states (A) S4 only (B) S2 & S4 only (C) S1 & S4 only (D) S1, S3 & S4 only
Which of the following is true? S1: If there is a cycle in RAG then there will be a deadlock S2: If there is a cycle in RAG where all the resources are havinng single instance then there will be a deadlock S3: Unsafe state results in deadlock S4: Deadlock states is subset of unsafe states (A) S4 only (B) S2 & S4 only (C) S1 & S4 only (D) S1, S3 & S4 only
answered Sep 7 in CO and Architecture Himanshu Kumar Gupta 406 views
0 votes
3 answers
24
NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle.
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle.
answered Sep 7 in CO and Architecture Sanandan 127 views
2 votes
4 answers
26
ISRO2018-34
Micro program is: the name of a source program in micro computers set of microinstructions that defines the individual operations in response to a machine-language instruction a primitive form of macros used in assembly language programming a very small segment of machine code
Micro program is: the name of a source program in micro computers set of microinstructions that defines the individual operations in response to a machine-language instruction a primitive form of macros used in assembly language programming a very small segment of machine code
answered Sep 7 in CO and Architecture Sanandan 971 views
0 votes
2 answers
28
Microprogramming
A micro program control unit is required to generate a total of 25 control signals. Assume that during any micro instruction, at most two control signals are active. The number of bits required in the control word to generate the required ... this question I am asking about horizontal microprogramming) previous year gate question link:https://gateoverflow.in/2754/gate1996-2-25
A micro program control unit is required to generate a total of 25 control signals. Assume that during any micro instruction, at most two control signals are active. The number of bits required in the control word to generate the required control signals ... In this question I am asking about horizontal microprogramming) previous year gate question link:https://gateoverflow.in/2754/gate1996-2-25
answered Sep 6 in CO and Architecture Sanandan 338 views
3 votes
2 answers
30
gatebook test
Suppose the functions F and G can be computed in 8 and 3 nanoseconds by functional units UF and UG, respectively. Given three instances of UF and three instances of UG, it is required to implement the computation F(G(Xi)) for 1 ≤ i ≤ 13. A control Unit selects next task/s ... this computation is ( in nanoseconds): (A) 28 (B) 33 (C) 43 (D) 49 my answer is 43 but gatebook answer is 49.
Suppose the functions F and G can be computed in 8 and 3 nanoseconds by functional units UF and UG, respectively. Given three instances of UF and three instances of UG, it is required to implement the computation F(G(Xi)) for 1 ≤ i ≤ 13. A control Unit selects next task/s and ... complete this computation is ( in nanoseconds): (A) 28 (B) 33 (C) 43 (D) 49 my answer is 43 but gatebook answer is 49.
answered Sep 5 in CO and Architecture Amit puri 244 views
1 vote
3 answers
31
ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
answered Sep 5 in CO and Architecture Sanandan 745 views
0 votes
4 answers
32
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
answered Sep 5 in CO and Architecture Sanandan 287 views
4 votes
2 answers
33
CO Addressing
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be ..... Plz formulate a generic solution for this with diagram .
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be ..... Plz formulate a generic solution for this with diagram .
answered Sep 5 in CO and Architecture Sanandan 424 views
18 votes
2 answers
34
GATE2005-66
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$\begin{array}{clcl} \text{(1)} &\text{$A[I] = B[J]$} & \qquad\text{(a)} &\text{Indirect addressing} \\ \text{(2)} &\text{while $(^*A\text{+ ... $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$\begin{array}{clcl} \text{(1)} &\text{$A[I] = B[J]$} & \qquad\text{(a)} &\text{Indirect addressing} \\ \text{(2)} &\text{while $ ... $(1, c), (2, c), (3, b)$ $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$
answered Sep 4 in CO and Architecture Sanandan 2.6k views
0 votes
3 answers
35
MadeEasy Test Series: CO & Architecture - Addressing Modes
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an ... executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an interrupt occurs during the execution of $I-6$, ... When $I-6$ is executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63
answered Sep 4 in CO and Architecture Sanandan 478 views
2 votes
4 answers
36
ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
answered Sep 4 in CO and Architecture Sanandan 776 views
0 votes
4 answers
37
NIELIT 2017 DEC Scientist B - Section B: 47
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
answered Sep 4 in CO and Architecture Sanandan 304 views
1 vote
4 answers
39
NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
answered Sep 4 in CO and Architecture Sanandan 293 views
2 votes
2 answers
40
Gateforum Tests
Can anybody explain in brief how to solve such numericals.
Can anybody explain in brief how to solve such numericals.
answered Sep 3 in CO and Architecture sachin486 208 views
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