Recent questions and answers in CO and Architecture

+16 votes

1 answer

1

difference between compulsory miss, conflict miss and capacity miss
I want to clearly understand the difference between compulsory miss, conflict miss and capacity miss what I understood is compulsory miss: when a block of main memory is trying to occupy fresh empty line of cache, it ... Because in associative mapping, no block of main memory tries to occupy already filled line. is this correct?

answered 1 day ago in CO and Architecture by Ansaaa24 (75 points) | 9.2k views

+25 votes

7 answers

2

GATE2014-3-43
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies $1$ ns, $2.2 $ ns, $2$ ns, $1$ ... of this program on the old and the new design are $P$ and $Q$ nanoseconds, respectively. The value of $P/Q$ is __________.

answered 1 day ago in CO and Architecture by Satbir Boss (19.5k points) | 6.4k views

+76 votes

8 answers

3

GATE2004-47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The ... instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

answered 2 days ago in CO and Architecture by shadabeqbal (43 points) | 19.3k views

+13 votes

2 answers

4

GATE2009-29
Consider a $4$-way set associative cache (initially empty) with total $16$ cache blocks. The main memory consists of $256$ blocks and the request for memory blocks are in the following order: $0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.$ Which one of the following memory block will NOT be in cache if LRU replacement policy is used? $3$ $8$ $129$ $216$

answered 3 days ago in CO and Architecture by Satbir Boss (19.5k points) | 3.6k views

+15 votes

3 answers

5

GATE1998-18
For a set-associative Cache organization, the parameters are as follows: $\begin{array}{|c|l|} \hline \text {$t _c$} & \text{Cache Access Time }\\\hline \text{$ ... $n = k\times m$ is a non-zero integer and $1 < m \leq l$. Give the value of the hit ratio for $l = 1$.

answered 4 days ago in CO and Architecture by Satbir Boss (19.5k points) | 1.9k views

+8 votes

5 answers

6

GATE2018-5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III

answered 5 days ago in CO and Architecture by JashanArora Junior (827 points) | 2.9k views

0 votes

2 answers

7

GATE1987-4b
What is cache memory? What is rationale of using cache memory?

answered 6 days ago in CO and Architecture by Satbir Boss (19.5k points) | 184 views

0 votes

2 answers

8

Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

answered Oct 15 in CO and Architecture by jeeruajay (21 points) | 100 views

+46 votes

5 answers

9

GATE2017-1-51
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first ... $10$ times. The number of conflict misses experienced by the cache is _________ .

answered Oct 13 in CO and Architecture by JashanArora Junior (827 points) | 11.5k views

+3 votes

4 answers

10

UGCNET-June2016-III-5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement

answered Oct 12 in CO and Architecture by Shailendra_ (241 points) | 1.6k views

+44 votes

8 answers

11

GATE2017-1-25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

answered Oct 10 in CO and Architecture by JashanArora Junior (827 points) | 7k views

+3 votes

3 answers

12

UGCNET-June-2019-II-11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed

answered Oct 10 in CO and Architecture by Shagun Singh (233 points) | 215 views

+26 votes

3 answers

13

GATE2017-2-29
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average memory access time ( ... $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$

answered Oct 5 in CO and Architecture by Nitesh Singh 2 Active (3k points) | 8k views

0 votes

3 answers

14

GATE1991-01,iv
Using the 8087 arithmetic coprocessor with the 8086 CPU requires that the 8086 CPU is operated ............

answered Oct 5 in CO and Architecture by sagar_gupta (11 points) | 433 views

+1 vote

2 answers

15

UGCNET-AUG2016-III-5
In _____ addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction. Register direct Register indirect Base indexed Displacement

answered Oct 5 in CO and Architecture by Shailendra_ (241 points) | 271 views

+24 votes

3 answers

16

GATE2004-20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV

answered Oct 5 in CO and Architecture by Shailendra_ (241 points) | 2.4k views

+10 votes

3 answers

17

GATE2004-65
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is: $8, 12, 0, 12, 8$. $2$ $3$ $4$ $5$

answered Oct 5 in CO and Architecture by Rudr Pawan (121 points) | 4k views

0 votes

1 answer

18

CO & architecture
The arithmetic expression : (a + b) * c - d / e * * f is to be evaluated on a two-address machine, where each operands, the number of registers required to evaluate this expression is ______. The number of memory access of operand is __________.

answered Oct 4 in CO and Architecture by Ashish2215 (11 points) | 49 views

+5 votes

8 answers

19

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

answered Oct 4 in CO and Architecture by `JEET Loyal (8.2k points) | 2.4k views

+31 votes

4 answers

20

GATE2006-74
Consider two cache organizations. First one is $32 \hspace{0.2cm} KB$ $2-way$ set associative with $32 \hspace{0.2cm} byte$ block size, the second is of same size but direct mapped. The size of an address is $32 \hspace{0.2cm} bits$ in both cases . A $2-to-1$ ... . The value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$

answered Oct 3 in CO and Architecture by Nitesh Singh 2 Active (3k points) | 8k views

+3 votes

3 answers

21

Hardware requirement in 16-way Set Associative Cache
Cache size 32 KB Block size = 32 Bytes Address size = 28 bit. Associativity of Cache = 16 Determine what is the hardware requirement to design the 16-way set associative cache. Hardware requirement -> Mux, Comparator, Demux, Decoder, Encoder ... lines are 5. 4) 64 And gates 5) 1 OR gate input line = 64 Someone, please verify these attributes??

answered Oct 3 in CO and Architecture by Nitesh Singh 2 Active (3k points) | 741 views

+1 vote

1 answer

22

self doubt
Main memory=512 words. block size=8 words. cache size =32 words There is an array A[100] and each element is 4 words then what is the hit ratio for the following loop. for(i=0;i<=9;i++) { for(j=0;j<=9;j=j+2) { A[i][j]=A[i][j]+20; } }

answered Oct 2 in CO and Architecture by darshan-at (17 points) | 96 views

+1 vote

2 answers

23

Minimum clock cycle

answered Oct 2 in CO and Architecture by Pavan Kumar 5 (37 points) | 167 views

0 votes

2 answers

24

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

answered Oct 2 in CO and Architecture by Sahin (171 points) | 342 views

0 votes

1 answer

25

#madeeasy test series

answered Oct 1 in CO and Architecture by jha_ashwaniii (41 points) | 21 views

0 votes

1 answer

26

Made easy
Consider a 5 stage pipeline which allows overlapping of all instructions except branch instructions.The target of branch instructions is not available until the branch instruction is completed. Let each stage delay is 20 ns and there are 30% branch instructions. What is performance gain of pipeline over non pipeline

answered Oct 1 in CO and Architecture by jha_ashwaniii (41 points) | 52 views

0 votes

1 answer

27

carl hamacher(chapter 2 )
in the underline statement it is given that higher performance can be achieved if each instruction occupy one word???how it is true??what happen when two instruction occupy in single word???

answered Oct 1 in CO and Architecture by Siddhant1211 (11 points) | 42 views

+1 vote

1 answer

28

types of miss in cache
a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity misses?

answered Sep 28 in CO and Architecture by shubham gupta 4 (49 points) | 367 views

0 votes

1 answer

29

best book for computer architecture specially for numerical part
which is the best book for computer architecture specially for numerical part like pipelining , desigining of large memory from small memory etc out of following 1)morris mano 2)W. stallings 3)Hamacher 4) John P Hayes 5)K. Hwang or any other

answered Sep 27 in CO and Architecture by `JEET Loyal (8.2k points) | 308 views

+31 votes

3 answers

30

GATE2008-35
For inclusion to hold between two cache levels $L_1$ and $L_2$ in a multi-level cache hierarchy, which of the following are necessary? $L_1$ must be write-through cache $L_2$ must be a write-through cache The associativity of $L_2$ must be greater than that of $L_1$ The $L_2$ cache must be at least as large as the $L_1$ cache IV only I and IV only I, II and IV only I, II, III and IV

answered Sep 26 in CO and Architecture by meetesh06 (21 points) | 6.7k views

0 votes

1 answer

31

Control dependencies
Consider a pipelined processor having 5 stages. The stage delays are 2, 3, 2.5, 3.2, 2.5ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding branch target address. Processor starts fetching new instruction when the conditional branch outcome is known. 20% of instructions are conditional branch, then calculate the execution time for 1000 instructions?

answered Sep 24 in CO and Architecture by abhi97.dutta (19 points) | 243 views

+2 votes

1 answer

32

WEST BENGAL SET COMPUTER SCIENCE

answered Sep 23 in CO and Architecture by Satbir Boss (19.5k points) | 35 views

+1 vote

1 answer

33

WEST BENGAL SET COMPUTER SCIENCE

answered Sep 22 in CO and Architecture by `JEET Loyal (8.2k points) | 47 views

0 votes

6 answers

34

DMA
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. What percentage of time is the CPU in busy mode (approximately)?

answered Sep 22 in CO and Architecture by mahabir10 (57 points) | 1.1k views

0 votes

2 answers

35

ISRO 2006- ECE
If the memory chip size is 256 x 1 bits, then the number of chips required to make up 1K bytes of memory is a) 32 b) 24 c) 12 d) 8

answered Sep 21 in CO and Architecture by Vk Gautam (11 points) | 602 views

0 votes

1 answer

36

#pipeline
Consider execution of 100 instructions on a 5 stage pipeline. let P be the probability of an instruction being branch. The value of P such that speed up is atleast 4 is_____(assume each stage takes 1 cycle to perform its task and branch is predicted on forth stage of the pipeline)

answered Sep 21 in CO and Architecture by Akash Ghosh (357 points) | 121 views

0 votes

1 answer

37

Branch Target Address
In a normal 5-stage pipeline, when is the branch target address available? There are some sources which say that the address is available after the MEM stage, but go on to say that it can be found out after the ID stage if we put in an extra ... in which they assumed that the address is available after the 4th stage. Is that the approach to be followed for all the questions?

answered Sep 21 in CO and Architecture by Akash Ghosh (357 points) | 61 views

0 votes

1 answer

38

Pipelining
Why pipelining cannot operate at its maximum theoretical speed? Maximum theoretical is when we say that it takes same time to process an instruction in pipeline and non pipeline circuit. So why pipelining cannot operate at its maximum theoretical speed?

answered Sep 21 in CO and Architecture by Akash Ghosh (357 points) | 41 views

+1 vote

1 answer

39

MadeEasy Test Series 2019: CO & Architecture - Pipelining
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23) [closed]

answered Sep 21 in CO and Architecture by Akash Ghosh (357 points) | 122 views

+14 votes

3 answers

40

GATE2008-IT-81
Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1$ MB of main memory, a word size of $1$ $byte$, a block size of $128$ words and a cache size of $8$ $KB$. While accessing the ... location $0C795H$ by the CPU, the contents of the TAG field of the corresponding cache line is: $000011000$ $110001111$ $00011000$ $110010101$

answered Sep 21 in CO and Architecture by PRANAV M (241 points) | 1.8k views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Recent questions and answers in CO and Architecture

Recent Posts

Recent Blog Comments