Recent questions and answers in CO and Architecture

+27 votes

4 answers

1

GATE2007-54
In a simplified computer the instructions are: $\begin{array}{|l|l|} \hline \text {OP $R _j , R _i$} & \text{Perform $R _j $OP $R _i$ and store the result in register $R _j$ } \\\hline \text{OP $m,R _i$} & \text{Perform $val$ OP $ ... of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block? $2$ $3$ $5$ $6$

answered 5 hours ago in CO and Architecture by JashanArora (93 points) | 3.7k views

0 votes

1 answer

2

minimum number of registers
Consider the following expression and identify minimum number of registers required to implement the following expression : (a-b)+(e+(c-d))/f Can anyone please give the theory or notes of prerequisites -, how to solve these questions. The solution of the above ... adding R1 to the R2 and result is stored back into R1 since R1=R1+R2. Number of registers used is only 3.

answered 3 days ago in CO and Architecture by Ram Swaroop Active (3.9k points) | 59 views

0 votes

1 answer

3

AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.

answered 5 days ago in CO and Architecture by gourav94240 (65 points) | 86 views

+43 votes

7 answers

4

GATE2017-1-25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

answered 5 days ago in CO and Architecture by Pratyush Priyam Kuan (45 points) | 6.8k views

+1 vote

2 answers

5

How many address operations are possible
A computer has 40 bit instruction code . It uses one register operand and one memory operand .There are 128 general purpose regsiters and 256 M bytes of RAM If there are n 2 address operations which uses both register and memory then how many one address operations are possible a) (16-n)x 2^7 b)(32-n)x 2^6 c)64x 2^18 d)none

answered Aug 12 in CO and Architecture by piyuskmr (11 points) | 437 views

0 votes

1 answer

6

Consider a memory of 8 words per block.If 2 clock cycle are required to transfer address from CPU to main memory

answered Aug 11 in CO and Architecture by aditi19 Active (4k points) | 304 views

0 votes

1 answer

7

computer organization
A CPU, which addresses the data through its 5 registers in one of 14 different modes, is to be designed to support 10 arithmetic instructions, 15 logic instructions, 20 data moving instructions and 10 branch instructions of these instructions 20%, 60%, 60% and 50% are ... are double operand type. What is the minimum size of CPU instruction word? (A)18 (B)19 (C)20 (D)21

answered Aug 9 in CO and Architecture by heatx09 (11 points) | 92 views

0 votes

3 answers

8

Instruction Execution
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in ... for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18

answered Aug 9 in CO and Architecture by raju paul (231 points) | 172 views

+3 votes

3 answers

9

Interrupt
GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routine As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the ... am having confusion between option A and C... For hardware interrupt option A is suitable and for software interrupt option C

answered Aug 9 in CO and Architecture by ayushsomani (215 points) | 376 views

0 votes

1 answer

10

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

answered Aug 9 in CO and Architecture by raju paul (231 points) | 186 views

+1 vote

2 answers

11

GATE1987-2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an $I/O$ device is usually faster in memory-mapped-$I/O$ scheme than in $I/O$-mapped -$I/O$ scheme.

answered Aug 8 in CO and Architecture by Arnabh Gangwar (115 points) | 327 views

0 votes

2 answers

12

Memory Access-self doubt
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples

answered Aug 8 in CO and Architecture by raju paul (231 points) | 72 views

+1 vote

2 answers

13

ISRO2013-ECE 2s compliment number
The two numbers represented in signed 2s complement form are P= 11101101 and Q= 11100110. If Q is subtracted from P, the value obtained in signed 2s complement form is: a) 1000001111 b) 00000111 c)11111001 d) 111111001

answered Aug 7 in CO and Architecture by ushamya (483 points) | 533 views

+23 votes

4 answers

14

GATE1991-03,iii
03. Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: (iii) The total size of address space in a virtual memory system is limited by: the length of MAR the available secondary storage the available main memory all of the above none of the above

answered Aug 5 in CO and Architecture by Kush j (11 points) | 3.5k views

0 votes

3 answers

15

MadeEasy Test Series: CO & Architecture - Speedup
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by $20$%. The overall speedup achieved if the ratio of the ... operation used to take twice the time taken by fixed point operation in the original design(upto $2$ decimal places is __________.

answered Aug 4 in CO and Architecture by alok_patel (17 points) | 193 views

0 votes

2 answers

16

Ace Test Series: CO & Architecture - SpeedUp In Pipeline
Consider a nonpipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is

answered Aug 4 in CO and Architecture by alok_patel (17 points) | 288 views

0 votes

1 answer

17

Ace Test Series: CO & Architecture - Secondary Memory

answered Aug 4 in CO and Architecture by raju paul (231 points) | 69 views

+7 votes

2 answers

18

ISRO2017-21
A cache memory needs an access time of 30 ns and main memory 150 ns, what is average access time of CPU (assume hit ratio = 80%)? 60 ns 30 ns 150 ns 70 ns

answered Aug 3 in CO and Architecture by Ansaaa24 (29 points) | 7.3k views

+1 vote

1 answer

19

The L2 and L3 cache memories are divided into a blocks of 5 words.
Suppose there is a system which has 3 levels of cache i.e L1, L2 and L3. The access times of L1, L2 and L3 cache memories are 100 ns/word, 150 ns/word, and 250 ns/word respectively. The L2 and L3 cache memories are divided ... are 80% and 90% respectively. What is the average access time? A. 103ns B. 108ns C. 220ns D. 112ns

answered Aug 3 in CO and Architecture by raju paul (231 points) | 249 views

0 votes

1 answer

20

Associative Mapping
Why Tag Bits is equals to Block Bits in Associative Mapping ?

answered Aug 1 in CO and Architecture by ayushsomani (215 points) | 347 views

0 votes

2 answers

21

Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(

answered Jul 29 in CO and Architecture by KULDEEP SINGH 2 Junior (857 points) | 66 views

+1 vote

1 answer

22

Gateforum Test Series: CO & Architecture - Microprogramming

answered Jul 29 in CO and Architecture by KULDEEP SINGH 2 Junior (857 points) | 76 views

0 votes

4 answers

23

MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)

answered Jul 28 in CO and Architecture by raju paul (231 points) | 258 views

0 votes

2 answers

24

MadeEasy Test Series: CO & Architecture - I/O Handling
#plz check??

answered Jul 28 in CO and Architecture by raju paul (231 points) | 91 views

0 votes

1 answer

25

MadeEasy Subject Test: CO & Architecture - Dma

answered Jul 27 in CO and Architecture by raju paul (231 points) | 45 views

0 votes

1 answer

26

MadeEasy Subject Test: CO & Architecture - Dma

answered Jul 27 in CO and Architecture by raju paul (231 points) | 29 views

+3 votes

1 answer

27

Pipelining
Consider 4 stage instruction pipeline where different instructions are spending different cycles at different stages shown below: S1 S2 S3 S4 I1 1 3 2 1 I2 1 1 3 2 I3 3 1 1 1 I4 1 2 1 1 The following loop is executed in the pipeline for ... The number of cycles saved using the loop level parallelism over without loop level parallelism to executed the above program is _______ (in cycles).

answered Jul 26 in CO and Architecture by smosh (11 points) | 817 views

0 votes

1 answer

28

Effective Access Time
A Computer uses two level Cache L1 and L2 and in 2000 memory references there are 320 misses in L1 and 150 misses in L2. If Miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time in L2 is 10 clock cycle .What is average memory access time ? 3.6 cycles 5.4 cycles 25.06 cycles 4.8 cycles

answered Jul 24 in CO and Architecture by blackcloud (79 points) | 93 views

0 votes

1 answer

29

standrard co question with a bit of confusion
Considering hierarchical method,is my this equation correct? Assuming tlb access time as 0 ns EMAT = 300 [memory access time] + 0.2*(300*2)[2 level page table] + 0.2 * (500) Average instruction execution time = Emat + 200. = 720 ns.

answered Jul 20 in CO and Architecture by raju paul (231 points) | 81 views

0 votes

1 answer

30

DMA,interrupts
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.

answered Jul 19 in CO and Architecture by Neeraj Jetha (13 points) | 90 views

+2 votes

2 answers

31

Cache mapping
A byte-addressable computer has a small data cache capable of holding eight 32 bit words each cache block consists of one 32 bit word. When a given program is executed the processor reads data sequentially from the following hex addresses :200,204,208,20C ... ,2F4 this pattern is repeated four times. Assume that cache is initially empty. If direct mapping is used compute the hit ratio

answered Jul 17 in CO and Architecture by Vandana sharma (11 points) | 69 views

0 votes

1 answer

32

ROM(self doubts)
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits)

answered Jul 15 in CO and Architecture by Jacob4999 (21 points) | 20 views

0 votes

1 answer

33

Indirect Addressing Mode
Consider an instruction of indirect addressing mode. What are the number of memory references by the processor when instruction is a computation that requires a single operand and when it is an unconditional branch instruction respectively ?? 3,3 3,2 2,2 4,3 I believe the answer is B Correct me

answered Jul 15 in CO and Architecture by Jacob4999 (21 points) | 30 views

+1 vote

1 answer

34

GATE1988-9iii
In the program scheme given below indicate the instructions containing any operand needing relocation for position independent behaviour. Justify your answer. ...

answered Jul 15 in CO and Architecture by Arjun Veteran (416k points) | 126 views

0 votes

2 answers

35

Sum of Data dependencies
$I_1 : MUL \ \ \ \ \ R_1, R_2, R_3$ // $R_1 \leftarrow R_2 \times R_3$ $I_2 : ADD \ \ \ \ \ R_4, R_4, R_1$ $I_3 : MUL \ \ \ \ \ R_1, R_5, R_6$ $I_2 : SUB \ \ \ \ \ R_4, R_4, R_1$ Sum of RAW, WAR and WAW dependencies is _____.

answered Jul 14 in CO and Architecture by Ram Swaroop Active (3.9k points) | 60 views

0 votes

2 answers

36

Madeeasy- Types of Dependencies
Please clarify along with the names.

answered Jul 14 in CO and Architecture by Ram Swaroop Active (3.9k points) | 69 views

+4 votes

1 answer

37

Dependency VS Hazard
Consider following program is executed on a 5 stage RISC pipeline and stages are IF, ID, EX, MA, WB. IF = Instruction Fetch ID = Instruction Decode and fetch register EX = Execution Stage MA = Memory Access WB = Write back register file Program: ... and Hazards.(There is no Structural Dependency) My Answers -> Dependencies = 6, hazards = 3. Someone verify these answer.

answered Jul 14 in CO and Architecture by Ram Swaroop Active (3.9k points) | 335 views

+1 vote

2 answers

38

UGCNET-June-2019-II-49
A processor can support a maximum memory of $4$ GB where memory is word addressable and a word is $2$ bytes. What will be the size of the address bus of the processor? At least $28$ bits At least $2$ bytes At least $31$ bits Minimum $4$ bytes

answered Jul 11 in CO and Architecture by Arnabh Gangwar (115 points) | 26 views

+1 vote

2 answers

39

UGCNET-June-2019-II-20
Suppose that a computer program takes $100$ seconds of execution time on a computer with multiplication operation responsible for $80$ seconds of this time. How much do you have to improve the speed of the multiplication operation if you are asked to execute this program four times faster? $14$ times faster $15$ times faster $16$ times faster $17$ times faster

answered Jul 11 in CO and Architecture by Arnabh Gangwar (115 points) | 34 views

+1 vote

2 answers

40

UGCNET-June-2019-II-19
How many address lines and data lines are required to provide a memory capacity of $16 K \times 16$? $10, \:4$ $16, \: 16$ $14, \:16$ $4, \:16$

answered Jul 11 in CO and Architecture by Arnabh Gangwar (115 points) | 60 views

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