Recent questions and answers in CO & Architecture

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1

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

asked 1 day ago in CO & Architecture by DIYA BASU (241 points) | 12 views

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2

Self Doubt
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK

asked 1 day ago in CO & Architecture by DIYA BASU (241 points) | 10 views

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1 answer

3

Self Doubt
Can someone provide me with the link of the answer key for Computer Organization(Zaky and Hamacher). Thanking you in advance:)

answered 2 days ago in CO & Architecture by Anchit Gupta (41 points) | 16 views

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4

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache

asked 3 days ago in CO & Architecture by DIYA BASU (241 points) | 13 views

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5

Self-Doubt Priority interrupts
Under the SOFTWARE METHOD – POLLING heading. What is the meaning of this line? “In this method, all interrupts are serviced by branching to the same service program”. https://www.geeksforgeeks.org/priority-interrupts-sw-polling-daisy-chaining/

asked 3 days ago in CO & Architecture by amitqy Active (1.4k points) | 13 views

+1 vote

1 answer

6

Cache mapping
A byte-addressable computer has a small data cache capable of holding eight 32 bit words each cache block consists of one 32 bit word. When a given program is executed the processor reads data sequentially from the following hex addresses :200,204,208,20C ... ,2F4 this pattern is repeated four times. Assume that cache is initially empty. If direct mapping is used compute the hit ratio

answered 4 days ago in CO & Architecture by Yash4444 (433 points) | 58 views

+1 vote

1 answer

7

#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

answered 5 days ago in CO & Architecture by utsavdey95 (133 points) | 41 views

0 votes

2 answers

8

ACE TEST SERIES

answered 5 days ago in CO & Architecture by Aks9639 (255 points) | 30 views

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4 answers

9

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

answered 6 days ago in CO & Architecture by Tuhin Dutta Loyal (9.1k points) | 2.6k views

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0 answers

10

#MulticoreVSParallel
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?

asked 6 days ago in CO & Architecture by Reshu $ingh (329 points) | 28 views

0 votes

4 answers

11

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

answered Feb 12 in CO & Architecture by Tuhin Dutta Loyal (9.1k points) | 1.8k views

0 votes

1 answer

12

#BookRecommendation
For Memory Addressing and Pipelining portion which standard book should I refer? Or any good resource to have crystal clear understanding,please suggest.

answered Feb 11 in CO & Architecture by aambazinga Active (3.2k points) | 30 views

0 votes

1 answer

13

SELF DOUBT
In Single Precision floating point number when E=0 and M not equals to 0 it represents a fractional form..(BiAS=+127) when writing the decimal form why do we right (-1)^S * (1.M) * 2^(-126) instead of (-1)^S * (1.M) * 2^(-127)??

answered Feb 11 in CO & Architecture by _shashi (255 points) | 20 views

0 votes

1 answer

14

GATE-2000
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that (A) T1 <= T2 (B) T1 >= T2 (C) T1 < T2 (D) T1 is T2 plus the time taken for one ... instruction would take to execute in a non-pipelined system as it has only one unit.(I AM COMPARING ONLY THE TIME TAKEN BY A SINGLE INSTRUCTION).

answered Feb 11 in CO & Architecture by prashant jha 1 Active (4.1k points) | 22 views

+18 votes

7 answers

15

GATE2017-2-53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is _______

answered Feb 8 in CO & Architecture by Suneel Padala Junior (733 points) | 3k views

+2 votes

1 answer

16

COA : Pipelining Calculating CPI
Solving Pipeling Question from https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf ReIterating the Relevant text here ------------------- You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. Calculate ... 1.4) = 1.7 The solution mentions 0.2*2.4 + 0.05*3.4 how did 2.4 and 3.4 come here?

answered Feb 7 in CO & Architecture by Heet Sankesara (11 points) | 138 views

0 votes

2 answers

17

GATE2019-2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF

answered Feb 7 in CO & Architecture by Shaik Masthan Veteran (55.8k points) | 1.8k views

0 votes

2 answers

18

Machine instructions
Q15 I am having confusion regarding indirect bit(mode bit) .Are mode bit used in deciding number of operations possible?

answered Feb 7 in CO & Architecture by Whitewalker (23 points) | 171 views

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2 answers

19

gate 2019

answered Feb 6 in CO & Architecture by pratekag (457 points) | 368 views

0 votes

1 answer

20

gate 2019
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits

answered Feb 5 in CO & Architecture by hello_friends (21 points) | 299 views

0 votes

1 answer

21

self doubt
How to do:(1000)base3 – (121)base3 without converting them to base 10 the final answer should be in base3

answered Feb 4 in CO & Architecture by prashant jha 1 Active (4.1k points) | 51 views

0 votes

1 answer

22

#address lines
Memory=1GB 16 bit processor System is byte addressable How many address lines required? I think 30 should be the ans as though processor is of 16bit but system is byte addressable so it can address only 1 byte using 1 line. Please clarify.

answered Feb 4 in CO & Architecture by Rackson Active (1.8k points) | 52 views

0 votes

1 answer

23

Gate cse 2019
A certain processor deploy a single level-cache, the cache block size is 8 words, word size is 4 bytes, memory system uses 60mHz clock, to service a cache miss, the memory controller first takes 1 clock cycle to accept starting address of the block, ... bandwidth for the memory system when the program on the processor issues a series of read operation is _____________( yt s s )

answered Feb 4 in CO & Architecture by Markzuck Junior (635 points) | 852 views

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0 answers

24

SELF DOUBT
what is (120)base 10=( ? )base 64 ??

asked Feb 4 in CO & Architecture by DIYA BASU (241 points) | 81 views

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0 answers

25

COA booth algorithm self doubt
Why we do right shift in booth algorithm? I know the working of booths algorithm. Suppose we have multiplicand M = 01011 and multiplier Q = 01110 We can write Q as (2^4 - 2^1). So multiplication reduces to 2^4(M) + 2(-M) Now booths algorithm rules ... ^4(M) + 2(-M) we multiply by 16 and 2 which requires left shift. So how is booths algorithm working with right shift ?

asked Feb 4 in CO & Architecture by kd..... Junior (851 points) | 62 views

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0 answers

26

self doubt
Main memory=512 words. block size=8 words. cache size =32 words There is an array A[100] and each element is 4 words then what is the hit ratio for the following loop. for(i=0;i<=9;i++) { for(j=0;j<=9;j=j+2) { A[i][j]=A[i][j]+20; } }

asked Feb 3 in CO & Architecture by DIYA BASU (241 points) | 83 views

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0 answers

27

self doubt
Main memory=512 words. block size=8 words. cache size =32 words what is tag,line no.,block offset bits

asked Feb 3 in CO & Architecture by DIYA BASU (241 points) | 55 views

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0 answers

28

self doubt
https://gateoverflow.in/2308/gate1993-11 This question can also be solved as a probability question where the random space contains (M1),(M1,M2),(M1,M2,M3) and let X be the random variable which gives the time for any of the three options selected from the ... space and correspondingly we give the PMF for each time selected and then we find the expectation?? Am I correct with my logic??

asked Feb 2 in CO & Architecture by DIYA BASU (241 points) | 27 views

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1 answer

29

Self doubt
Can anyone please explain in simple terms indexed, relative and base register addressing modes?

answered Feb 2 in CO & Architecture by krmanish043 Junior (581 points) | 32 views

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1 answer

30

SELF DOUBT
If main memory size=128KB. cache size 16KB . block size 256B. And memory is word addressable each word is 4B . Then is the address divided into : tag=3bits. line no=6 bits block offset=6 bits???(PLEASE VERIFY) We use DIRECT MAPPING.

answered Feb 2 in CO & Architecture by Satbir Active (4.9k points) | 29 views

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0 answers

31

Addresing modes
A computer has 64 bit instruction and 8 bit address.if there are 32 no of 3 address instruction and 248 no of 2 address instruction.how many 1 address instruction possible??

asked Feb 2 in CO & Architecture by Ssgmailcom (7 points) | 30 views

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0 answers

32

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1 in CO & Architecture by newdreamz a1-z0 Active (1.6k points) | 46 views

0 votes

3 answers

33

NIELIT Scientist-B Dec 2017_15
A stacked organized computer has which of the following instructions ? (A) zero-address (B) one-address (C) two-address (D) three-address

answered Feb 1 in CO & Architecture by kranti (11 points) | 175 views

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0 answers

34

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1 in CO & Architecture by Aman Janko (47 points) | 20 views

0 votes

0 answers

35

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1 in CO & Architecture by learner_geek Active (3.7k points) | 35 views

0 votes

0 answers

36

made easy test series
please provide a detailed solution

asked Feb 1 in CO & Architecture by Vignaneswarkrishna (167 points) | 48 views

0 votes

0 answers

37

Cache
Please tell what happens to hit rate, hit time, compulsory miss rate, conflict miss rate, capacity miss rate, miss time on : 1. Increasing Cache size 2. Increasing Block size 3. Increasing number of lines 4. Increasing Associativity

asked Jan 31 in CO & Architecture by Balaji Jegan Active (4.8k points) | 47 views

+10 votes

3 answers

38

#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32

answered Jan 31 in CO & Architecture by indrajeet meena (23 points) | 2.1k views

+1 vote

1 answer

39

Multiprocessor Systems
The incorrect match is (for n > 1) : SISD Model of computer : 1 control unit and 1 ALU SIMD Model of computer : 1 control unit and n ALUs MISD Model of computer : n control unit and n ALUs MIMD Model of computer : n control unit and 1 ALU

answered Jan 31 in CO & Architecture by JAYKISHAN (93 points) | 67 views

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0 answers

40

Cache acess
I know the acess time to a sequential acess cache is given as Hitrate*(Cache acess time)+ Miss rate*(Cachec acess time + Mem acess time) Now in question if they explicitly say in case of miss data is obtained from memory and put into cache and again ... , will my formula change Hirate(Cache acess time)+ Misseate* ( Cache acess time+ Mem acess time + Cache acess time) pls help me

asked Jan 31 in CO & Architecture by Aravind Adithya 1 (213 points) | 14 views

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