Recent questions and answers in CO and Architecture

59 votes

2 answers

1

GATE2017-2-45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... instruction fetch and $40$% are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________

The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... are for instruction fetch and $40$% are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________

answered 1 day ago in CO and Architecture CheeseCuBES 15.4k views

57 votes

3 answers

2

GATE2004-63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$

Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $\begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\hline \text{MOV $R_1, ... has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$

answered 3 days ago in CO and Architecture StoneHeart 14.9k views

46 votes

5 answers

3

GATE2007-71
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$

Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$

answered 3 days ago in CO and Architecture StoneHeart 11.4k views

40 votes

12 answers

4

GATE2005-80
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in ... $2$ $3$ $4$ $5$

The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR ... $2$ $3$ $4$ $5$

answered 3 days ago in CO and Architecture StoneHeart 12.4k views

106 votes

16 answers

5

GATE2004-47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The ... instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB ... average instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

answered 4 days ago in CO and Architecture thewolf 34k views

51 votes

11 answers

6

GATE2005-70
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

answered 5 days ago in CO and Architecture tusharSingh 21.5k views

36 votes

11 answers

7

GATE2004-IT-50
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by $\text{20%}$ and the speed of a fixed point unit has been increased by $\text{10%}$. What is the overall speedup achieved if the ratio of the number of floating point ... used to take twice the time taken by the fixed point operation in the original design? $1.155$ $1.185$ $1.255$ $1.285$

In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by $\text{20%}$ and the speed of a fixed point unit has been increased by $\text{10%}$. What is the overall speedup achieved if the ratio of the number of floating point operations ... used to take twice the time taken by the fixed point operation in the original design? $1.155$ $1.185$ $1.255$ $1.285$

answered Jan 14 in CO and Architecture reboot 10k views

3 votes

2 answers

8

Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB

A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB

answered Jan 14 in CO and Architecture eshita1997 825 views

2 votes

3 answers

9

Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

answered Jan 13 in CO and Architecture eshita1997 304 views

0 votes

1 answer

10

general doubt on pipelining
we do forwarding from WB stage to EX or from WB to MEM stage??

we do forwarding from WB stage to EX or from WB to MEM stage??

answered Jan 10 in CO and Architecture jhhkjhjkb 156 views

69 votes

11 answers

11

GATE2007-80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main memory starting ... the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$

Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main memory starting from ... of the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$

answered Jan 5 in CO and Architecture StoneHeart 15.6k views

4 votes

4 answers

12

ISRO2020-5
An array of $2$ ...

An array of $2$ ...

answered Jan 1 in CO and Architecture ayush.5 797 views

0 votes

4 answers

13

NIELIT 2016 MAR Scientist C - Section C: 19
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack

When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack

answered Dec 30, 2020 in CO and Architecture paami461 289 views

1 vote

2 answers

14

Calculate sum of (WAR, RAW and WAW) dependencies instructions.
Consider the following instructions. I 1 : R 1 = 100 I 2 : R 1 = R 2 + R 4 I 3 : R 2 = R 4 + 25 I 4 : R 4 = R 1 + R 3 I 5 : R 1 = R 1 + 30 Calculate sum of (WAR, RAW and WAW) dependencies the above instructions. (a) 10 (c) 6 (b) 12 (d) 8

Consider the following instructions. I 1 : R 1 = 100 I 2 : R 1 = R 2 + R 4 I 3 : R 2 = R 4 + 25 I 4 : R 4 = R 1 + R 3 I 5 : R 1 = R 1 + 30 Calculate sum of (WAR, RAW and WAW) dependencies the above instructions. (a) 10 (c) 6 (b) 12 (d) 8

answered Dec 28, 2020 in CO and Architecture eshita1997 1.6k views

0 votes

2 answers

15

Pipeline Efficiency
A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

answered Dec 26, 2020 in CO and Architecture StoneHeart 854 views

67 votes

7 answers

16

GATE2017-1-51
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first ... $10$ times. The number of conflict misses experienced by the cache is _________ .

Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access ... $10$ times. The number of conflict misses experienced by the cache is _________ .

answered Dec 25, 2020 in CO and Architecture StoneHeart 20k views

5 votes

3 answers

17

Pipelining (Hamacher)
A pipeline processor has two branch delay slots. An optimizing compiler can fill one of these slots 85% of the time and can fill the second slot 20% of the time. What percentage improvement in performence achieved by this optimization, assuming 20% of the instruction executed are branch instruction?

A pipeline processor has two branch delay slots. An optimizing compiler can fill one of these slots 85% of the time and can fill the second slot 20% of the time. What percentage improvement in performence achieved by this optimization, assuming 20% of the instruction executed are branch instruction?

answered Dec 25, 2020 in CO and Architecture StoneHeart 1.3k views

29 votes

3 answers

18

GATE1999-2.22
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic

The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic

answered Dec 23, 2020 in CO and Architecture Gaurav nitkkriit 4.7k views

43 votes

8 answers

19

GATE2006-42
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions ... is: $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$

A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following ... is: $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$

answered Dec 22, 2020 in CO and Architecture anurag_yo 10.7k views

18 votes

4 answers

20

MadeEasy Test Series: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 50 cycles. The hit time of L$_2$ cache is 10 cycles. The ... with given misses = 1800 stall cycles = 1800-1250 = 550 number of stalls/instruction= 550/200 = 2.75 please verify

Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 50 cycles. The hit time of L$_2$ cache is 10 cycles. The hit time of the L$_1$ cache is 5 ... 1250 number of cycles with given misses = 1800 stall cycles = 1800-1250 = 550 number of stalls/instruction= 550/200 = 2.75 please verify

answered Dec 16, 2020 in CO and Architecture reboot 2k views

1 vote

2 answers

21

gate 2019
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits

Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits

answered Dec 12, 2020 in CO and Architecture AKSHAY PRATAP SINGH 533 views

0 votes

1 answer

22

8085 microprocessor
Consider the following set of instructions executed by 8085 microprocessor MOV H,20 MOV L,10 MOV E,00 XCHG After the execution, the contents of E register will be ______________ (integer value only). i dont know how to solve this and ques. based on 8085 microprocessor can be asked in GATE??

Consider the following set of instructions executed by 8085 microprocessor MOV H,20 MOV L,10 MOV E,00 XCHG After the execution, the contents of E register will be ______________ (integer value only). i dont know how to solve this and ques. based on 8085 microprocessor can be asked in GATE??

answered Dec 6, 2020 in CO and Architecture Aditi28 621 views

1 vote

2 answers

23

UGCNET-Nov2017-iii-5
Which of the following is correct statement? In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words. The isolated I/O method isolates memory and I/O addresses so ... transfer of data the two units share a common clock. In synchronous serial transmission of data the two units have different clocks.

Which of the following is correct statement? In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words. The isolated I/O method isolates memory and I/O addresses so that memory ... serial transfer of data the two units share a common clock. In synchronous serial transmission of data the two units have different clocks.

answered Dec 6, 2020 in CO and Architecture vipin.gautam1906 1k views

39 votes

4 answers

24

GATE2005-69
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$

A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$

answered Dec 3, 2020 in CO and Architecture yashhoskere 10.1k views

80 votes

9 answers

25

GATE2013-45
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... taken during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... is taken during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

answered Dec 2, 2020 in CO and Architecture emsugandh 24.9k views

2 votes

1 answer

26

Computer Architecture-Secondary Memory
Susheel is setting up a website. He bought a fancy new hard disk which advertises: an 8 ms average seek time. 10000 RPM or roughly 6 ms per rotation. a2 ms overhead for each disk operation. a transfer speed of 10,000,000 bytes per ... have an average size of 8000 bytes. How much time will it take on an average to read a random HTML file from the disk?

Susheel is setting up a website. He bought a fancy new hard disk which advertises: an 8 ms average seek time. 10000 RPM or roughly 6 ms per rotation. a2 ms overhead for each disk operation. a transfer speed of 10,000,000 bytes per second Susheel had enough ... HTML files have an average size of 8000 bytes. How much time will it take on an average to read a random HTML file from the disk?

answered Dec 2, 2020 in CO and Architecture prajjwalsingh_11 277 views

34 votes

3 answers

27

GATE2010-33
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ADD and SUB ... $13$ $15$ $17$ $19$

A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ADD and SUB instructions, ... $13$ $15$ $17$ $19$

answered Nov 29, 2020 in CO and Architecture StoneHeart 11.5k views

44 votes

8 answers

28

GATE2009-28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$S _2$} & \textbf {$ ... is the number of cycles needed to execute the following loop? For $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$S _2$} & \textbf {$S _3$} & \textbf{$S _4 ... $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

answered Nov 29, 2020 in CO and Architecture StoneHeart 17k views

34 votes

3 answers

29

GATE2004-IT-47
Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop: for (i = 1; i < = 1000; i++) {I1, I2, I3, I4} where the time taken (in ns) by instructions $I1$ to $I4$ for stages $S1$ to $S4$ ... $I1$ for $i = 2$ will be available after $\text{11 ns}$ $\text{12 ns}$ $\text{13 ns}$ $\text{28 ns}$

Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop: for (i = 1; i < = 1000; i++) {I1, I2, I3, I4} where the time taken (in ns) by instructions $I1$ to $I4$ for stages $S1$ to $S4$ ... $I1$ for $i = 2$ will be available after $\text{11 ns}$ $\text{12 ns}$ $\text{13 ns}$ $\text{28 ns}$

answered Nov 29, 2020 in CO and Architecture StoneHeart 6.9k views

57 votes

8 answers

30

GATE2000-12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. ... and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. Under ... , and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

answered Nov 29, 2020 in CO and Architecture StoneHeart 8.2k views

21 votes

3 answers

31

GATE1988-2-ii
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer. ...

Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer. ...

answered Nov 28, 2020 in CO and Architecture StoneHeart 1.5k views

0 votes

1 answer

32

UGCNET-Oct2020-II: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$

Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$

answered Nov 26, 2020 in CO and Architecture Sanjay Sharma 65 views

77 votes

7 answers

33

GATE2005-65
Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$ uses indirect addressing mode. $A$ and $B$ are memory ... destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$

Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$ uses indirect addressing mode. $A$ and $B$ are memory addresses ... destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$

answered Nov 26, 2020 in CO and Architecture StoneHeart 19.2k views

1 vote

1 answer

34

UGCNET-Oct2020-II: 81
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct ... false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true

Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct answer from the ... are false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true

answered Nov 25, 2020 in CO and Architecture Sanjay Sharma 40 views

6 votes

3 answers

35

Gateoverflow Computer architecture 2 exam question
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit ... per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.

Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit time in L1 cache is 10 cycles ... number of stall cycles per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.

answered Nov 23, 2020 in CO and Architecture shashankpal 581 views

0 votes

1 answer

36

UGCNET-Oct2020-II: 43
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$

Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$

answered Nov 23, 2020 in CO and Architecture Sanjay Sharma 61 views

0 votes

1 answer

37

UGCNET-Oct2020-II: 7
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$

A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$

answered Nov 22, 2020 in CO and Architecture Sanjay Sharma 97 views

0 votes

1 answer

38

UGCNET-Oct2020-II: 6
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$

The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$

answered Nov 21, 2020 in CO and Architecture Sanjay Sharma 125 views

40 votes

3 answers

39

GATE2015-3-47
Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$ ... above statements is/are correct? Only S1 is true Only S2 is true Only S1 and S3 are true Only S2 and S3 are true

Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri. $I_1$: ADD ... of the above statements is/are correct? Only S1 is true Only S2 is true Only S1 and S3 are true Only S2 and S3 are true

answered Nov 21, 2020 in CO and Architecture shashankpal 9k views

0 votes

1 answer

40

Addressing Instructions
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?

Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?

answered Nov 21, 2020 in CO and Architecture Jan Bhardwaj 182 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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