Recent questions and answers in CO and Architecture

Recent questions and answers in CO and Architecture

0 votes

1 answer

1

can 0 address instruction be used in accumulator based architecture? how?
In 0-address instruction, no address is specified within an instruction along with the Opcode, so is it possible to use 0-address instruction in accumulator based architecture?

Divya2199 answered in CO and Architecture May 7

35 views

42 votes

5 answers

2

GATE CSE 2014 Set 1 | Question: 9
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in ... to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________

manikantsharma answered in CO and Architecture May 4

by manikantsharma

12.8k views

0 votes

1 answer

3

ISRO | ISRO CS 2020 | Question 78
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block: Case 1 Case 2 t1 = a + b; t2 = c + d; t2 = c + d; t3 = e - t2; t3 = e - t2; t1 = a + b; t4 ... by how many MOV instructions ? (A) Case 2, 2 (B) Case 2, 3 (C) Case 1, 2 (D) Case 1, 3 (E) None of these

rd8794 answered in CO and Architecture Apr 23

by rd8794

89 views

0 votes

0 answers

4

a microprocssor has a data bus with 64 lins and an address bus with 32 lines the maximum number of bits that can be stored in the memory is

fru asked in CO and Architecture Apr 22

by fru

62 views

0 votes

4 answers

5

NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor? Static memory Dynamic memory ROM None of the option

s_dr_13 answered in CO and Architecture Mar 31

808 views

0 votes

4 answers

6

NIELIT 2017 DEC Scientist B - Section B: 38
Which of the following is false? The smallest and fastest computer imitating brain working is called quantum computer. A computer with a speed of around $100$ million instructions per second with the word length of around $64$ bits is known as super computer. The term Exa-byte $= 1024$ Tera Bytes. None of the options.

s_dr_13 answered in CO and Architecture Mar 31

935 views

33 votes

4 answers

7

GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing

manikantsharma answered in CO and Architecture Mar 13

by manikantsharma

8.0k views

29 votes

5 answers

8

GATE CSE 1996 | Question: 1.16, ISRO2016-42
Relative mode of addressing is most relevant to writing: Co – routines Position – independent code Shareable code Interrupt Handlers

manikantsharma answered in CO and Architecture Mar 13

by manikantsharma

9.6k views

5 votes

2 answers

9

Addressing Mode
"The Address Part of the Index Addressing mode Instruction must set to zero,to behave like Register Indirect Mode Instruction" IS IT A VALID STATEMENT ?

manikantsharma answered in CO and Architecture Mar 13

by manikantsharma

547 views

4 votes

2 answers

10

GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.

sainarendra answered in CO and Architecture Feb 24

1.3k views

3 votes

2 answers

11

GATE CSE 2022 | Question: 23
A cache memory that has a hit rate of $0.8$ has an access latency $10 \; \text{ns}$ and miss penalty $100 \; \text{ns}.$ An optimization is done on the cache to reduce the miss rate. However, the optimization results ... (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _______________.

Deba2020 answered in CO and Architecture Feb 21

1.4k views

2 votes

1 answer

12

GATE CSE 2022 | Question: 44
Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ and a word length of $16 \; \text{bits.}$ During the execution of a program, four data ... only $\text{R}$ and $\text{S}$ reside in the cache. Every access to $\text{R}$ evicts $\text{Q}$ from the cache.

Shaik Masthan answered in CO and Architecture Feb 15

by Shaik Masthan

816 views

3 votes

1 answer

13

GATE CSE 2022 | Question: 14
Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache and $\text{WT}$ ... cache to main memory. A read miss in $\text{WB}$ will never lead to eviction of a dirty block from $\text{WB}.$

Kanwae Kan answered in CO and Architecture Feb 15

1.2k views

2 votes

2 answers

14

GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput? $\text{DMA}$ based $\text{I/O}$ transfer Interrupt driven $\text{I/O}$ transfer Polling based $\text{I/O}$ transfer Programmed $\text{I/O}$ transfer

`JEET answered in CO and Architecture Feb 15

by `JEET

680 views

3 votes

0 answers

15

#pipeline #self doubt
Consider a 5—stage pipeline processor used to execute 200 number of instructions and among those 100 instructions cause 3 stall cycles each. What is the total cycles required for these operation if CPI is not equal to one.

jayadev asked in CO and Architecture Feb 3

149 views

4 votes

3 answers

16

Made Easy Test Series
Consider the following statements: S1 : Direct mapped caches do not need a cache block replacement policy, whereas fully associative cache need. S2 : Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct?

Vishal_kumar98 answered in CO and Architecture Jan 31

by Vishal_kumar98

214 views

45 votes

10 answers

17

GATE CSE 2001 | Question: 2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The ... $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$

Nitesh_Yadav answered in CO and Architecture Jan 24

by Nitesh_Yadav

15.1k views

0 votes

1 answer

18

MADE-EASY Full Length Test
Options were: 823 55 223 31 Please give detailed solution.

amitraj123 answered in CO and Architecture Jan 23

150 views

69 votes

4 answers

19

GATE CSE 2017 Set 2 | Question: 45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... and $40\%$ are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________

Nitesh_Yadav answered in CO and Architecture Jan 22

by Nitesh_Yadav

22.3k views

2 votes

2 answers

20

Made Easy Test Series
Consider 5 stage pipelined processor has instruction fetch (IF), Instruction decode (ID), Operand fetch (OF), Perform operation (PO) and Write operand (WB) stages. The IF, ID, OF and WB stages takes 1 clock cycle each for any ... instructions respectively. How many clock cycles needed to execute the above sequence of instruction, where operand forwarding from PO to PO?

tirth_patel answered in CO and Architecture Jan 21

156 views

0 votes

1 answer

21

Applied Test Series
Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields : the first byte contains the opcode and the remainder is an immediate operand or an operand address. What is the maximum directly addressable memory capacity (in Megabytes)? consider memory as byte addressable.

Aditya_ answered in CO and Architecture Jan 21

100 views

0 votes

1 answer

22

computer organization
Is non-linear pipe lining in gate 2022???

aaa 1 answered in CO and Architecture Jan 21

by aaa 1

116 views

2 votes

2 answers

23

Made Easy Test Series
Consider a pipeline consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline y' contain the same number of stages but EX stage is divided into 2 ... the program contain 20% of the instructions which are memory based instructions, what is the ratio of speed-up of x to speed-up of y?

Vishal_kumar98 answered in CO and Architecture Jan 20

by Vishal_kumar98

170 views

1 vote

0 answers

24

Made Easy Test Series
Consider a fully associative cache with 6 cache blocks (0 to 5) and the following sequence of memory block requests: 5, 4, 29, 18, 21, 7, 25, 18, 16, 35, 45, 22, 7, 19 If LRU replacement policy is used, which cache block is used for memory block 19? Assume initially 6 blocks are placed in a cache according to lexicographic order of cache index.

LRU asked in CO and Architecture Jan 20

by LRU

148 views

0 votes

1 answer

25

ACE CBT 2018
An instruction pipelined processor has five stages namely, instruction fetch (F), instruction decode (D), Instruction execution (E), memory Access for operand (M) and write Back (W) with stage latencies of 1 ns, 2ns, 2 ns, 1 ns, 1 ns respectively. To gain ... (in ns) using new design over old design is __________. I am getting 99 but the answer provided is 96. Can you please verify.

Amit puri answered in CO and Architecture Jan 19

278 views

1 vote

2 answers

26

Appllied Gate Test Series
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for read, hit ratio of 0.9 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?

Shrusti answered in CO and Architecture Jan 18

113 views

0 votes

1 answer

27

General Doubt
Can each operand have a separate mode in a double operand instruction?

aaa 1 answered in CO and Architecture Jan 17

by aaa 1

127 views

0 votes

0 answers

28

GeeksForGeeks AIM 2 - instruction format
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based ... . How many bits are in address selection field, address field and the size of control memory in words respectively?

atulcse asked in CO and Architecture Jan 15

137 views

0 votes

1 answer

29

Testbook test series
Can anyone please solve this?

amitraj123 answered in CO and Architecture Jan 15

125 views

1 vote

0 answers

30

Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____

LRU asked in CO and Architecture Jan 14

by LRU

152 views

0 votes

2 answers

31

made easy test series - instruction format
Consider a hypothetical CPU which supports 16-bit instruction, 64 registers and 1 KB memory space. If there exist 12 2-address instructions which use register references and 12 1-address memory reference instructions then how many 0-address instructions are possible?

girish13 answered in CO and Architecture Jan 14

151 views

66 votes

8 answers

32

GATE CSE 2016 Set 2 | Question: 33
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

Kabir5454 answered in CO and Architecture Jan 14

13.7k views

1 vote

0 answers

33

made easy test series - cache addressing
Consider a 4-way set associative cache of 64 KB used in a 32-bit CPU, organized into 32-word blocks. System supports 64 GB RAM. Cache is designed with a write back protocol to handle the updation issues. In each line a valid bit is present to specify the status of a block. What is the size (in bits) of a tag directly in the cache controller?

atulcse asked in CO and Architecture Jan 13

166 views

0 votes

3 answers

34

Applied Test Series:
Need help Anyone?

Kabir5454 answered in CO and Architecture Jan 13

198 views

0 votes

1 answer

35

Applied Test Series
Consider a processor that includes a base with indexing addressing mode. Suppose an instruction is encountered that employs this addressing mode and specifies a displacement of 1970, in decimal. Currently the base and index register contain the decimal numbers 48,022 and 8, respectively. What is the address of the operand?

aaa 1 answered in CO and Architecture Jan 10

by aaa 1

176 views

0 votes

2 answers

36

Self doubt Pipelining
Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i<=1) {I1,I2,I3,I4} where i=0. Time (ns) taken by the instruction I1 to I4 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 I1 1 1 2 1 1 I2 1 2 1 1 1 I3 1 2 2 1 1 I4 2 1 2 1 1 Output of I4 will be available at $_____$.

kysewtts answered in CO and Architecture Jan 9

130 views

0 votes

1 answer

37

Applied Test Series
Consider the following sequence of instructions Add #20,R0,R1 Mul #3,R2,R3 And # ... fetch(other stages also) requires only one clock cycle. Number of cycles required to complete the given sequence of instructions are_____

Isha_99 answered in CO and Architecture Jan 8

115 views

0 votes

1 answer

38

Applied Test Series
Consider the following sequence of instructions: LOAD R4, 0(R8) AND R1, R5, R2 OR R1, R1, R3 OR R2, R2, R7 ADD R3, R2, R1 STORE R3, 0(R8) Number of cycles required to complete the given sequence of instructions in a 5 stage (IF, ID, EX, Mem, WB) RISC processor with operand forwarding_____

Isha_99 answered in CO and Architecture Jan 8

148 views

1 vote

1 answer

39

Applied Test Series
Consider following assembly-language program: 1: MOV R3, R7 2: LOAD R8, (R3) 3: ADD R3, R3, 4 4: LOAD R9, (R3) 5: BNE R8, R9, L3 The sum of WAW, RAW, and WAR dependencies from the given code are_________

LRU asked in CO and Architecture Jan 8

by LRU

95 views

0 votes

1 answer

40

Applied Gate Test Series
How to solve this?

imkeshav asked in CO and Architecture Jan 6

162 views

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