Recent questions and answers in CO and Architecture - GATE Overflow

+1 vote

1 answer

1

COA: Cache Accesss Time
Little confusion with these questions. What will be o/p for these two questions one with Write back and the other is Write through. 1.)A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache ... average access time? What will be the default technique ( write-allocate and no write-allocate)followed for Hierarchal and Simultaneous access ?

answered 1 day ago in CO and Architecture by Shikha shree | 155 views

+1 vote

1 answer

2

Indirect index addressing mode
I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode

answered 1 day ago in CO and Architecture by SANGAMESH017 | 199 views

+1 vote

1 answer

3

Ace Test Series: CO & Architecture - DMA And Bus Architecture
Answer is D please explain

answered 2 days ago in CO and Architecture by Mohnish | 95 views

+1 vote

3 answers

4

GATE1988-9i
The following program fragment was written in an assembly language for a single address computer with one accumulator register: LOAD B MULT C STORE T1 ADD A STORE T2 MULT T2 ADD T1 STORE Z Give the arithmetic expression implemented by the fragment.

answered 2 days ago in CO and Architecture by pratapvidhu1 | 302 views

+2 votes

1 answer

5

Gateforum Tests
Can anybody explain in brief how to solve such numericals.

answered 5 days ago in CO and Architecture by Mohnish | 154 views

+1 vote

1 answer

6

RAW, WAR, WAW hazards
J1: R1 = 100 J2: R1 = R2 + R4 J3: R2 = R4 + 25 J4: R4 = R1 + R3 J5: R1 = R1 + 30 Give the no of RAW, WAR and WAW hazards

answered Jun 29 in CO and Architecture by Sainath Mandavilli | 723 views

+2 votes

1 answer

7

Pipeline Efficiency
The speed up of a pipelined processor is $5.4,$ operating at $2$ GHZ frequency with efficiency $82\%$. What will be no. of stages available in this processor$?$

answered Jun 26 in CO and Architecture by GATE2021 | 158 views

0 votes

1 answer

8

Pipeline Made easy

answered Jun 21 in CO and Architecture by GATE2021 | 98 views

+1 vote

1 answer

9

ME TEST SERIES
for calculating % why it is divided by 122 ?

answered Jun 11 in CO and Architecture by pranab09 | 97 views

+4 votes

4 answers

10

GATE2020-CS-44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.

answered Jun 11 in CO and Architecture by TheAnteamatter | 1.9k views

+2 votes

2 answers

11

what is meant by cache is physically addressed and cache is virtually addressed

answered Jun 7 in CO and Architecture by Adarsh Pandey | 1.8k views

+41 votes

9 answers

12

GATE2005-70
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

answered Jun 6 in CO and Architecture by Tiklu_95 | 16k views

+32 votes

6 answers

13

GATE2008-38
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: before effective address calculation has started during effective address calculation after effective address calculation has completed after data cache lookup has completed

answered Jun 5 in CO and Architecture by topper98 | 5.5k views

+73 votes

5 answers

14

GATE2014-1-44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed through a cache ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$

answered Jun 5 in CO and Architecture by Animesh Sinha | 9.2k views

0 votes

1 answer

15

PIPELINING
Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2, $4, $2 ADD $1, $3, $5 SW $2, 20($4) ADD $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

answered Jun 4 in CO and Architecture by srestha | 91 views

0 votes

2 answers

16

made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____

answered Jun 4 in CO and Architecture by ummokkate | 143 views

+29 votes

4 answers

17

GATE2004-20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV

answered Jun 2 in CO and Architecture by Doraemon | 3.5k views

0 votes

2 answers

18

cpu has 24 bit instruction and program starts at 300(decimal)which is legal program counter: ISRO 2009 Q.35

answered Jun 2 in CO and Architecture by ProtonicRED | 596 views

0 votes

2 answers

19

Testbook Test Series: CO & Architecture - Microprogramming
# is it correct answer??? plz check

answered May 31 in CO and Architecture by Mitali gupta | 144 views

0 votes

1 answer

20

NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory has Lower bit density and higher power consumption Higher bit density and lower power consumption Lower bit density and lower power consumption None of the option

answered May 31 in CO and Architecture by Mohit Kumar 6 | 44 views

0 votes

1 answer

21

NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time is Same as the access time. Longer than the access time. Shorter than the access time. Multiple of the access time.

answered May 31 in CO and Architecture by Mohit Kumar 6 | 43 views

0 votes

1 answer

22

NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor? Static memory Dynamic memory ROM None of the option

answered May 31 in CO and Architecture by Mohit Kumar 6 | 40 views

0 votes

1 answer

23

NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle.

answered May 31 in CO and Architecture by Mohit Kumar 6 | 65 views

0 votes

4 answers

24

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

answered May 31 in CO and Architecture by Raju2021 | 133 views

+22 votes

3 answers

25

GATE2008-73
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bit$ virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows: double ... by the program are those to array $ARR$. The cache hit ratio for this initialization loop is: $0$% $25$% $50$% $75$%

answered May 31 in CO and Architecture by Kushagra गुप्ता | 2.5k views

0 votes

3 answers

26

Pipeline Execution time
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 are performing multiplications, where Excution state for addition take 1 clock cycle, multiplication take 3 clock cycles ... control hazard. The number of clock cycles required for execution of sequence of instructions are ________. Ans. 454

answered May 30 in CO and Architecture by Raju2021 | 967 views

+92 votes

13 answers

27

GATE2004-47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The ... instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

answered May 28 in CO and Architecture by Sheth Nisarg | 25.8k views

+54 votes

7 answers

28

GATE2016-1-32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.

answered May 28 in CO and Architecture by Sheth Nisarg | 10.6k views

+25 votes

4 answers

29

GATE2003-10, ISRO-DEC2017-41
For a pipelined CPU with a single ALU, consider the following situations The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand The execution of a conditional jump instruction The $j^{th}$ and ${j+1}^{st}$ instructions ... the ALU at the same time. Which of the above can cause a hazard I and II only II and III only III only All the three

answered May 27 in CO and Architecture by topper98 | 3.8k views

+27 votes

5 answers

30

GATE1987-1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode

answered May 21 in CO and Architecture by shivam001 | 4.4k views

0 votes

2 answers

31

NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options

answered May 19 in CO and Architecture by Hradesh patel | 132 views

+6 votes

2 answers

32

wrie through updation in cache
Consider a system with cache access time 20 ns and main memory access time 140 ns. If 60% operations are read operations and hit ratio is 90%. What is the effective access time if write through updation technique is used? (a) 75.2 ns (b) 76.4 ns (c) 83.2 ns (d) 84.4 ns

answered May 17 in CO and Architecture by Smarth | 1.2k views

+39 votes

4 answers

33

GATE2007-71
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$

answered May 15 in CO and Architecture by Kushagra गुप्ता | 8.1k views

+22 votes

3 answers

34

GATE2003-49
Consider the following assembly language program for a hypothetical processor A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; $B \leftarrow 0$ MOV C, #8 ; $C \leftarrow 8$ Z: CMP C, #0 ; compare C with 0 JZ ... same as its initial value? RRC A, #1 NOP ; no operation LRC A, #1; left rotate A through carry flag by one bit ADD A, #1

answered May 15 in CO and Architecture by Kushagra गुप्ता | 3.7k views

+24 votes

2 answers

35

GATE2003-48
Consider the following assembly language program for a hypothetical processor $A, B,$ and $C$ are $8-$bit registers. The meanings of various instructions are shown as comments. $\begin{array}{lll} & \text{MOV B, #0}&& \text{;} & \text{$ ... B after the program execution will be the number of $0$ bits in $A_0$ the number of $1$ bits in $A_0$ $A_0$ $8$

answered May 15 in CO and Architecture by Kushagra गुप्ता | 5.7k views

0 votes

1 answer

36

Ace Test Series: Digital Logic - ROM
I am getting (C). But answer given is (B). Where I have gone wrong?

answered May 14 in CO and Architecture by srestha | 667 views

+1 vote

1 answer

37

Word Addressable (GATE 2004)

answered May 13 in CO and Architecture by hacker_deb | 316 views

+1 vote

1 answer

38

Calculate number of times Zero Flag is Reset
I am getting 37.

answered May 13 in CO and Architecture by hacker_deb | 188 views

+34 votes

4 answers

39

GATE2014-1-9
A machine has a $32-bit$ architecture, with $1-word$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________

answered May 8 in CO and Architecture by shivam001 | 6.9k views

+47 votes

4 answers

40

GATE2016-2-31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each instruction must be ... If a program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.

answered May 8 in CO and Architecture by shivam001 | 7.8k views

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