Recent questions and answers in CO and Architecture - GATE Overflow

+54 votes

6 answers

1

GATE2017-1-51
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first ... $10$ times. The number of conflict misses experienced by the cache is _________ .

answered 5 hours ago in CO and Architecture by KrantiKumari (129 points) | 12.7k views

+21 votes

5 answers

2

GATE2006-81
A CPU has a $32$ $KB$ direct mapped cache with $128$ byte-block size. Suppose $A$ is two dimensional array of size $512 \times512$ with elements that occupy $8-bytes$ each. Consider the following two $C$ code segments, $P1$ and $P2$. $P1$: for (i=0; i<512; i++) { for (j=0; j< ... for $P2$ be $M2$. The value of the ratio $\frac{M_{1}}{M_{2}}$: $0$ $\frac{1}{16}$ $\frac{1}{8}$ $16$

answered 1 day ago in CO and Architecture by Raj Singh 1 (313 points) | 2.6k views

+12 votes

4 answers

3

#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32

answered 1 day ago in CO and Architecture by Sourajit25 Active (1.6k points) | 2.9k views

+1 vote

1 answer

4

ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $ADD, SUB$ and $MOV$. Consider $2$ ... is better in terms of memory accesses and by how many $MOV$ instructions ? Case $2,2$ Case $2,3$ Case $1,2$ Case $1,3$

answered 4 days ago in CO and Architecture by UNickAyush (11 points) | 152 views

+1 vote

1 answer

5

ISRO2020-6
A non-pipeined CPU has $12$ general purpose registers $(R0,R1,R2 ..,R12)$. Following operations are supported $ADD\ Ra,\ Rb,\ Rr$ Add $Ra$ to $Rb$ and store the result in $Rr$ $MUL\ Ra,\ Rb,\ Rr$ Multiply $Ra$ to $Rb$ and store the result in $Rr$ $MUL$ ... $R0,R1$ and $R2$ and the contents of these registers must not be modified. $5$ $6$ $7$ $8$

answered 4 days ago in CO and Architecture by venkatesh pagadala Junior (677 points) | 122 views

+1 vote

2 answers

6

ISRO2020-2
Statements associated with registers of a CPU are given. Identify the false statement. The program counter holds the memory address of the instruction in execution Only opcode is transferred to the control unit An instruction in the instruction register consists of the ... The value of the program counter is incremented by $1$ once its value has been read to the memory address register

answered 5 days ago in CO and Architecture by Tuhin Dutta Boss (10.5k points) | 127 views

+1 vote

1 answer

7

ISRO2020-3
Which of the following affects the processing power assuming they do not influence each other Data bus capability Address scheme Clock speed $3$ only $1$ and $3$ only $2$ and $3$ only $1,2$ and $3$

answered 5 days ago in CO and Architecture by Tuhin Dutta Boss (10.5k points) | 89 views

+2 votes

2 answers

8

ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits

answered 5 days ago in CO and Architecture by Tuhin Dutta Boss (10.5k points) | 168 views

+2 votes

1 answer

9

ISRO2020-5
An array of $2$ ...

answered 5 days ago in CO and Architecture by Tuhin Dutta Boss (10.5k points) | 112 views

+1 vote

1 answer

10

ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing

answered 5 days ago in CO and Architecture by `JEET Boss (18.8k points) | 133 views

+1 vote

2 answers

11

ISRO2020-46
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes? $1,280,000$ $1280$ $1250$ $128,000$

answered 5 days ago in CO and Architecture by Ashwani Kumar 2 Boss (16.3k points) | 150 views

+1 vote

1 answer

12

ISRO2020-43
Which of the following is an efficient method of cache updating Snoopy writes Write through Write within Buffered write

answered 5 days ago in CO and Architecture by `JEET Boss (18.8k points) | 104 views

+2 votes

1 answer

13

ISRO2020-49
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called True dependency Anti-dependency Output dependency Control Hazard

answered 5 days ago in CO and Architecture by `JEET Boss (18.8k points) | 83 views

+1 vote

1 answer

14

ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache

answered 5 days ago in CO and Architecture by `JEET Boss (18.8k points) | 63 views

+2 votes

2 answers

15

ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers does the processor has? $32$ $64$ $128$ $16$

answered 5 days ago in CO and Architecture by Ashwani Kumar 2 Boss (16.3k points) | 84 views

+2 votes

1 answer

16

ISRO2020-7
Consider a $5$- segment pipeline with a clock cycle time $20$ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$

answered 5 days ago in CO and Architecture by `JEET Boss (18.8k points) | 110 views

0 votes

2 answers

17

Chip Select
Ans. C

answered Jan 11 in CO and Architecture by jlimbasiya Junior (557 points) | 49 views

+1 vote

2 answers

18

ISRO2018-34
Micro program is: the name of a source program in micro computers set of microinstructions that defines the individual operations in response to a machine-language instruction a primitive form of macros used in assembly language programming a very small segment of machine code

answered Jan 9 in CO and Architecture by Arnabi Loyal (8k points) | 598 views

+1 vote

2 answers

19

ideal CPU memory
Consider a CPU that executes at a clock rate of 200MHZ(5ns per cycle)with a single level of cache .CPI execution (i.e) CPI with ideal memory is 1.1.Instruction mix are 50% arithmetic/logical ,30% load/store , 20% control instructions.Assume cache miss rate is 15%and a miss penalty of 5 cycles.The number of times CPU with ideal memory is faster when no miss occurs

answered Jan 8 in CO and Architecture by Anup dogrial (299 points) | 287 views

0 votes

2 answers

20

ME TEST SERIES
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probability of an instruction being a branch instruction then the value of p such that speed up is atleast 3 is ________. (Upto 2 decimal places)

answered Jan 8 in CO and Architecture by Anup dogrial (299 points) | 252 views

+1 vote

2 answers

21

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

answered Jan 8 in CO and Architecture by Anup dogrial (299 points) | 96 views

+3 votes

3 answers

22

ISRO2008-45
The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP ? it is level triggered it is negative edge triggered it is +ve edge triggered it is both +ve and -ve edges triggered

answered Jan 7 in CO and Architecture by `JEET Boss (18.8k points) | 1.8k views

+33 votes

8 answers

23

GATE2001-2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1}$, $A_{2}$, MDR, the bus and the ALU are $8$-$bit$ wide. SP and MAR are $16$-$bit$ registers. The MUX is of size $8 \times (2:1)$ ... $SP ← SP - 1$ How many CPU clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$

answered Jan 6 in CO and Architecture by Anony_XYZ (17 points) | 6.2k views

+16 votes

3 answers

24

GATE2005-IT-61
Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be present in the cache after the following sequence of memory block references if LRU policy is used for cache block replacement. Assuming that ... $7$ $9$ $16$ $55$ $0$ $5$ $7$ $9$ $16$ $55$ $3$ $5$ $7$ $9$ $16$ $55$

answered Jan 5 in CO and Architecture by chirudeepnamini Active (4.3k points) | 3k views

+7 votes

5 answers

25

ISRO2016-19
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is 3.2 3.0 2.2 2.0

answered Jan 5 in CO and Architecture by `JEET Boss (18.8k points) | 3.2k views

0 votes

2 answers

26

chain multiplication
what is the faster way to calculate in short time

answered Jan 5 in CO and Architecture by Debapaul (335 points) | 108 views

+16 votes

2 answers

27

difference between compulsory miss, conflict miss and capacity miss
I want to clearly understand the difference between compulsory miss, conflict miss and capacity miss what I understood is compulsory miss: when a block of main memory is trying to occupy fresh empty line of cache, it ... Because in associative mapping, no block of main memory tries to occupy already filled line. is this correct?

answered Jan 3 in CO and Architecture by Arjun Veteran (430k points) | 9.8k views

+38 votes

4 answers

28

GATE2015-1-38
Consider a non-pipelined processor with a clock rate of $2.5$ $GHz$ and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2$ $GHz$. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.

answered Jan 2 in CO and Architecture by `JEET Boss (18.8k points) | 9.7k views

+39 votes

4 answers

29

GATE2004-64
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ \begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size (in Words)} \\\hline \text{MOV $R_1,5000$} & ... clock cycles }\\\hline \end{array} The total number of clock cycles required to execute the program is $29$ $24$ $23$ $20$

answered Jan 2 in CO and Architecture by JashanArora Loyal (6.1k points) | 6.4k views

+44 votes

3 answers

30

GATE2008-71
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bi$t virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows: double ARR[ ... $ARR$. The total size of the tags in the cache directory is: $32$ $Kbits$ $34$ $Kbits$ $64$ $Kbits$ $68$ $Kbits$

answered Jan 2 in CO and Architecture by Akash Ghosh (433 points) | 7k views

+2 votes

3 answers

31

ISRO2018-6
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code: Multiply $E$ by $0.5$ to get $F$ Add $A$ and $B$ to get $E$ Add $B$ with $0.5$ to get ... sequence of execution is valid? B, C, D, A, E C, B, E, A, D A, B, C, D, E E, D, C, B, A

answered Jan 1 in CO and Architecture by Satbir Boss (23.7k points) | 1.4k views

+8 votes

5 answers

32

How much time will the processor be slowed down due to DMA activity?
A processor is fetching instructions at the rate of 1 MIPS.A DMA module is used to transfer characters to RAM from a device transmitting at 9600 bps.How much time will the processor be slowed down due to DMA activity? a)9.6 ms b)4.8 ms c)2.4 ms d)1.2 ms

answered Dec 31, 2019 in CO and Architecture by Sourajit25 Active (1.6k points) | 3.6k views

0 votes

0 answers

33

NTA NET DEC 2019 (microprocessor)

asked Dec 30, 2019 in CO and Architecture by Sanjay Sharma Boss (49.3k points) | 70 views

+3 votes

1 answer

34

NTA NET DEC 2019 (micro operation)
Match List I List II a) Micro operation (i) Specify micro operation b) Microprogrammed control unit (ii) Improve CPU utilization c) Interrupts (iii) Control Memory d) Micro instruction (Iv) Elementary operation performed on data stored in registers Choose the correct option from these given below 1) ... ii 3) a-iii , b-iv , c- i , d-ii 4) a-iii , b-iv , c-ii , d-i

answered Dec 27, 2019 in CO and Architecture by `JEET Boss (18.8k points) | 50 views

+47 votes

7 answers

35

GATE2000-12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. ... and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

answered Dec 27, 2019 in CO and Architecture by kshitij (279 points) | 5.2k views

+1 vote

2 answers

36

MadeEasy Subject Test: CO & Architecture - Dma
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?

answered Dec 24, 2019 in CO and Architecture by Prateekj9521 (77 points) | 252 views

0 votes

1 answer

37

MadeEasy Workbook: CO & Architecture - Dma
Consider a device of 1MBPS is operating in a cycle stealing mode of DMA .Whenever 16 B word is available it is transferred into memory in 4 microseconds. What is the % of time the processor is blocked due to DMA? a) 10% b) 20% c) 80% d) 90%

answered Dec 24, 2019 in CO and Architecture by Prateekj9521 (77 points) | 175 views

0 votes

2 answers

38

Number of 1 address instructions
How many maximum number of one address instructions possible?

answered Dec 23, 2019 in CO and Architecture by neeraj_bhatt (293 points) | 139 views

0 votes

3 answers

39

Number of 0 address instructions possible
How many maximum number of zero address instructions possible?

answered Dec 23, 2019 in CO and Architecture by neeraj_bhatt (293 points) | 120 views

+44 votes

4 answers

40

GATE2015-3-51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$. $\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline & \text{1}& \text{2} & \text{$3$} & \text{$4$} & \text{$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______

answered Dec 21, 2019 in CO and Architecture by Kushagra गुप्ता Active (4k points) | 13k views

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