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Recent questions and answers in CO and Architecture

22 votes
5 answers
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF
answered Jul 16 in CO and Architecture aloksingh017 7.7k views
17 votes
8 answers
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
answered Jul 16 in CO and Architecture aloksingh017 10.7k views
1 vote
2 answers
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
answered Jul 14 in CO and Architecture rish1602 365 views
2 votes
5 answers
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
answered Jul 8 in CO and Architecture Harshad_Shinde 1.7k views
4 votes
3 answers
In IEEE $754$ single floating point format, how many numbers can be represented in the interval [10, 16)? A. $2^{21}$ B. $3 * 2^{21}$ C. $5 * 2^{21}$ D. $2^{22}$
answered Jun 27 in CO and Architecture rish1602 882 views
34 votes
4 answers
Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence? Instruction fetch Operand fetch Conditional branch Initiation of interrupt service
answered Jun 23 in CO and Architecture sridhar15399 9.1k views
42 votes
7 answers
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $\text{25%}$ less time but incurs $\text{20%}$ more CPI (clock cycles per instruction) as compared to the program ... $P_1$. If the clock frequency of $P_1$ is $\text{1GHZ}$, then the clock frequency of $P_2$ (in GHz) is ______.
answered Jun 21 in CO and Architecture ShivangiChauhan 11.6k views
0 votes
2 answers
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
answered Jun 13 in CO and Architecture meentu 333 views
1 vote
2 answers
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
answered Jun 13 in CO and Architecture Arjun 932 views
1 vote
1 answer
A certain computer system was designed with cache memory of size $1$ Kbytes and main memory size of $256$ Kbytes. The cache implementation was fully associative cache with $4$ bytes per block. The CPU memory data path was $16$ ... Answer the following questions: What is the hit ratio? Suggest a change in the program size of model to improve the hit ratio significantly.
answered Jun 13 in CO and Architecture gatecse 321 views
0 votes
2 answers
2 votes
3 answers
answered Jun 6 in CO and Architecture PRIYANSHU10 1.1k views
43 votes
5 answers
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ I3: ADD $R1 \leftarrow R2 + R3$ I4: STORE ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4
answered Jun 4 in CO and Architecture Arjun 7.9k views
1 vote
5 answers
A byte addressable computer has a memory capacity of $2$^{m}$KB$ ($k$ bytes) and can perform $2$^{n}$ operations. An instruction involving $3$ operands and one operator needs maximum of: $3m$ bits $3m + n$ bits $m + n$ bits none of the above
answered May 24 in CO and Architecture manojkoppolu 2k views
53 votes
12 answers
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$
answered May 20 in CO and Architecture felics moses 1 24.7k views
5 votes
4 answers
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
answered May 18 in CO and Architecture manojkoppolu 2k views
0 votes
1 answer
Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.
answered May 17 in CO and Architecture Hira Thakur 6.5k views
0 votes
2 answers
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
answered May 17 in CO and Architecture Hira Thakur 402 views
0 votes
1 answer
3 votes
1 answer
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
answered May 16 in CO and Architecture Raavi Karthik 351 views
32 votes
9 answers
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting ... bandwidth for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec
answered May 16 in CO and Architecture Raavi Karthik 11.1k views
6 votes
5 answers
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while each subsequent word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
answered May 15 in CO and Architecture Raavi Karthik 7.1k views
1 vote
5 answers
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
answered May 13 in CO and Architecture 2017BITE043 701 views
50 votes
4 answers
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average memory access time (AMAT) of ... and $L_2$ respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$
answered May 10 in CO and Architecture ayugupcse 17.8k views
3 votes
2 answers
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ ... decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
answered May 5 in CO and Architecture raj26 1.1k views
30 votes
4 answers
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic
answered May 3 in CO and Architecture Deepak2323 5.6k views
77 votes
10 answers
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.
answered Apr 27 in CO and Architecture PRIYANSHU10 15.1k views
65 votes
8 answers
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ nanoseconds, $20$ ... from $L2$ cache to $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds
answered Apr 23 in CO and Architecture adeemajain 22.6k views
79 votes
8 answers
Consider a three word machine instruction $\text{ADD} A[R_0], @B$ The first operand (destination) $ A[R_0] $ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) $ @B $ uses indirect addressing mode. $A$ and $B$ are memory ... the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$
answered Apr 15 in CO and Architecture vnsahu1331 22k views
4 votes
3 answers
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
answered Apr 3 in CO and Architecture Nikhil_dhama 1.2k views
4 votes
2 answers
Suppose that an unpipelined processor has a cycle time of 25ns, and that it's data path is made up of modules with latencies of 2,3,4,7,3,2 and 4ns(in that order).In pipelining this processor ,it is not possible to rearrange the order of the modules(for examples, putting the register ... 1,what is the latency of the pipeline? (a). no latency (b). 35 ns latency (c). 40 ns latency (d). 56 ns latency
answered Mar 27 in CO and Architecture sauravgahlawat 1.8k views
0 votes
2 answers
Consider the following expression and identify minimum number of registers required to implement the following expression : (a-b)+(e+(c-d))/f Can anyone please give the theory or notes of prerequisites -, how to solve these questions. The solution of the above problem is :- ... performed by adding R1 to the R2 and result is stored back into R1 since R1=R1+R2. Number of registers used is only 3.
answered Mar 27 in CO and Architecture jatinmittal199510 531 views
0 votes
2 answers
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction execution in each of the ... in 4 clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.
answered Mar 25 in CO and Architecture Jash12xyz 518 views
8 votes
6 answers
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is 3.2 3.0 2.2 2.0
answered Mar 22 in CO and Architecture shantanumapari17 4.1k views
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