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1

Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help

asked 23 hours ago in CO & Architecture by Na462 Active (1.6k points) | 14 views

+1 vote

0 answers

2

Pipeline
Say Machine with 10ns click and takes 4 cycles for AlU and other operations. When we talk about the time taken by pipelined processor it is = the highest time taken by a stage + overhead We took the highest time only because we know that there is no stalling so ... plz explain why then CPI is one in all cases when stalls aren't there. And plz explain the cpi for non pipelined processor .

asked 1 day ago in CO & Architecture by Na462 Active (1.6k points) | 10 views

+20 votes

3 answers

3

GATE2006-09, ISRO2009-35
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)? 400 500 600 700

answered 1 day ago in CO & Architecture by akshat sinha (231 points) | 3.1k views

+10 votes

3 answers

4

GATE2018-50
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB), The IF, ID, OF and WB stages take 1 clock cycle each for ... no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____

answered 1 day ago in CO & Architecture by Mostafize Mondal (53 points) | 1.7k views

0 votes

1 answer

5

memory
In a two-level cache system, the access times of L1 and L2 are 3, 10 clock cycles respectively. The miss penalty from the L2 cache to main memory is 20 clock cycles. The miss rate of L1 cache is thrice that of L2. The average memory access time(AMAT) of this cache system is 4 cycles. The miss rates of L1 and L2 respectively are:

answered 4 days ago in CO & Architecture by sonveer tomar 1 Junior (885 points) | 62 views

0 votes

0 answers

6

memory
Consider a system with the average memory access time of a processor with one level (L1) cache is 2.8 clock cycles. If the required data present in L1-cache it can be accessed in 1 clock cycle otherwise it needs 85 clock cycles to get it from memory. If ... considered, with the access time of 6 clock cycles. What is the hit rate of L2-cache such that average memory access improved by 70%?

asked 4 days ago in CO & Architecture by Anshu Singh Suryavan (55 points) | 12 views

0 votes

1 answer

7

Addressing Mode
Adding a constant to the content of register Is it a)Immediate mode or b) Indexed mode?

answered 4 days ago in CO & Architecture by Deepakk Poonia (Dee) Active (2.8k points) | 40 views

+1 vote

0 answers

8

#sample_test_iitk
An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequence S experiences 1000 misses when it is passed through a 32 KB 8-way set- ... conflict misses that the sequence S experiences when it is passed through a 32 KB 8-way set-associative cache is ___________

asked 4 days ago in CO & Architecture by tapzo Junior (507 points) | 41 views

0 votes

2 answers

9

Trishna book for gate
In a micro programmed control unit, a control field of one address control instruction has to support two groups of control signals. In group 1 it is required to generate either one or none of the 32 control signals. In group 2 at most 5 from the remaining, what will be the number of bits needed for the control field? A 8. B 10. C 35. D 37.

answered 5 days ago in CO & Architecture by sonveer tomar 1 Junior (885 points) | 32 views

0 votes

1 answer

10

set associative mapping
a cahe has 64 KB capacity, 128 byte line, and is 4 way set associative. the system containing the cache uses 32 bit addresses. If the cache is write through, _____bits are reuired for each entry in the tag array, and total storage required is __________ for the tag array if LRU replacement policy is used. 20,974 21,456 10,572 21,456 none

answered 6 days ago in CO & Architecture by ASIM SIDDIQUI 3 (65 points) | 150 views

+4 votes

5 answers

11

ISRO-2013-15
A pipeline $P$ operating at $400$ MHz has a speedup factor of $6$ and operating at $70$% efficiency. How many stages are there in the pipeline? $5$ $6$ $8$ $9$

answered 6 days ago in CO & Architecture by Rohit Kumar 2 (207 points) | 3.2k views

+1 vote

1 answer

12

GATE_BOOK Q
A privileged instruction may be executed only while the hardware is in kernel mode. Which of the following is LEAST likely to be a privileged instruction? (A) An instruction that changes the value of the program counter (B) An instruction that sends output to a printer (C) An instruction that halts the CPU (D) An instruction that resets the computer’s timeofday clock

answered Apr 12 in CO & Architecture by shruti gupta1 (11 points) | 130 views

0 votes

0 answers

13

Semester exam
1) A two way set associative cache memory uses a block size of 4 words . The cache can accommodate a total of 2048 words from main memory. The main memory size is 128kx32. a) What is the size of the cache memory.

asked Apr 10 in CO & Architecture by PriyankaS (9 points) | 20 views

0 votes

0 answers

14

MCQs in Computer Science -Timothy Williams 5 edition [closed]

asked Apr 10 in CO & Architecture by DEEPAK PANDEY 1 (165 points) | 30 views

+2 votes

0 answers

15

Computer Architecture-Secondary Memory
Susheel is setting up a website. He bought a fancy new hard disk which advertises: an 8 ms average seek time. 10000 RPM or roughly 6 ms per rotation. a2 ms overhead for each disk operation. a transfer speed of 10,000,000 bytes per ... have an average size of 8000 bytes. How much time will it take on an average to read a random HTML file from the disk?

asked Apr 10 in CO & Architecture by satendra (121 points) | 33 views

0 votes

1 answer

16

Made easy class test
https://gateoverflow.in/?qa=blob&qa_blobid=698736926868685114

answered Apr 10 in CO & Architecture by sonveer tomar 1 Junior (885 points) | 52 views

0 votes

2 answers

17

I/O organization- Hamacher
Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus wires between the processor and different devices connected varies from 1 to ... . The input buffer needs 3 ns. set up time. What is maximum clock speed at which this bus can operate?

answered Apr 8 in CO & Architecture by Sambit Kumar Active (2k points) | 36 views

0 votes

4 answers

18

coa

answered Apr 8 in CO & Architecture by aakashpreetam (251 points) | 87 views

+1 vote

3 answers

19

vgate
why is B wrong? as far as i know DRAM has less number of gates and hence its cheaper. but static RAM contains many gates per bit

answered Apr 8 in CO & Architecture by aakashpreetam (251 points) | 48 views

+3 votes

1 answer

20

computer organization
Consider two cache organizations. The first one if $64 \text{ KB}$ way associative with $64\text{ byte}$ block size. The second one is of the $64 \text{ KB}$ direct mapped cache. The size of an address is $32\text{bits}$ in both ... between the hit latencies of both cache organizations (i.e. associative hit latency - direct mapped hit latency) (in nsec) is ________ .

answered Apr 6 in CO & Architecture by abhishekmehta4u Loyal (9.1k points) | 69 views

0 votes

0 answers

21

Secondary memory

asked Apr 6 in CO & Architecture by Prince Sindhiya (355 points) | 55 views

0 votes

0 answers

22

asked Apr 6 in CO & Architecture by Prince Sindhiya (355 points) | 79 views

0 votes

0 answers

23

There seem two version of carl hamacher books? which one to get?

asked Apr 6 in CO & Architecture by cynicthnkr (7 points) | 27 views

0 votes

1 answer

24

Videos for Computer Architecture
The Gate Overflow Page for CO&A(https://gatecse.in/co-architecture/) has a broken YouTube link and I could not find any other good video lectures for Computer Organization. Kindly suggest any online video lectures that would be useful for GATE preparation

answered Apr 5 in CO & Architecture by iarnav Loyal (6.5k points) | 46 views

0 votes

0 answers

25

Virtual Memory
Say i have a Cache with hit ratio 96% and access time 1ns and a memory with access time 10 ns Now by default we go for Sequential access instead of Parallel Now... Tavg = 0.96*(1) + 0.4*(1+10) this will be the answer rt? My doubt is For ... one to apply?? Like used in Question:- https://gateoverflow.in/788/gate2003-78 they have used First one instead of Second.Please help me out??

asked Apr 4 in CO & Architecture by Na462 Active (1.6k points) | 24 views

0 votes

0 answers

26

Virtual Memory
I have some doubt please listen me out an point where I am wrong if i am wrong.. Let's say I have a physically addressed cache, a TLB and 2 level page table memory.(page table present in memory) Cpu generated a Logical address then firstly by the ... in main memory we will access main memory directly not cache here right? Or will it check in cache first for the presence of page?

asked Apr 3 in CO & Architecture by Na462 Active (1.6k points) | 67 views

0 votes

1 answer

27

Computer Organization
Suppose we are given frequency of cpu say 2GHZ then 1/2GHZ will be the instruction cycle time rt? I.e time to complete one instruction. Is instruction cycle time and cpu cycle time the same thing?

answered Apr 1 in CO & Architecture by smsubham Loyal (6k points) | 29 views

0 votes

0 answers

28

test_series
i think minimum mantisa is 2^-20 and not .5

asked Mar 30 in CO & Architecture by mehul vaidya Junior (593 points) | 17 views

+1 vote

1 answer

29

pipelining confusion branching
A CPU has five-stage pipeline and runs at 2 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The ... . if this is correct then plz check the below link https://gateoverflow.in/210004/pipelining where i m doing wrong

answered Mar 30 in CO & Architecture by abhishekmehta4u Loyal (9.1k points) | 21 views

0 votes

2 answers

30

Average Memory Access Time Problem
A cache is having 60% hit ratio for read operation. Cache access time is 30 ns and main memory access time is 100 ns, 50% operations are read operation. What will be the average access time for read operation? (a) 50 ns (b) 58 ns (c) 100 ns (d) 70 ns

answered Mar 30 in CO & Architecture by Sandy Sharma (235 points) | 610 views

0 votes

2 answers

31

IEEE floating Point
In IEEE floationg point representation, the hexadecimal number $0xC0000000$ corresponds to ? $-3.0$ $-1.0$ $-4.0$ $-2.0$

answered Mar 30 in CO & Architecture by pankaj_vir Loyal (6.2k points) | 183 views

+1 vote

3 answers

32

The square of the binary number 1001 in hexadecimal is

answered Mar 30 in CO & Architecture by pankaj_vir Loyal (6.2k points) | 858 views

+1 vote

2 answers

33

pipelining
A CPU has five-stage pipeline where each stage takes $1\hspace{0.1cm}ns$, $2\hspace{0.1cm}ns$, $1.5\hspace{0.1cm} ns$, $3\hspace{0.1cm}ns$, $2.5\hspace{0.1cm} ns$. Instruction fetch happens in the first stage of the pipeline. A ... one clock cycle. $30\%$ of the instructions are conditional branches. Find the average execution time of the program for $1200$ instructions is ________.

answered Mar 30 in CO & Architecture by Sambit Kumar Active (2k points) | 126 views

0 votes

1 answer

34

tesr_series
I think answer is A , there is o need to divide Q by 4 as no of tags = Size of Main memory(P blocks) / Size of cache memory (Q blocks)

answered Mar 29 in CO & Architecture by abhishekmehta4u Loyal (9.1k points) | 22 views

+1 vote

0 answers

35

test series
can someone please answer this question i think answer is B subtraction of two n bit unsigned number will give result which is n bit only we also require 1 extra bit to hold borrow if in (A-B) , A<B

asked Mar 29 in CO & Architecture by mehul vaidya Junior (593 points) | 30 views

0 votes

1 answer

36

Self doubt
What is the difference between Performance, Throughput ,Efficiency and speedup??

answered Mar 27 in CO & Architecture by Sankha Narayan Bose (123 points) | 32 views

+2 votes

1 answer

37

UGCNET-Nov2017-ii-32
Consider the following assembly program fragment: stc mov al, 11010110b mov cl,2 rcl al,3 rol al, 4 shr al, cl mul cl The contents of the destination register ax (in hexadecimal ) and the status of Carry Flag (CF) after the execution of above instructions, are: ax =003CH; CF=0 ax=001EH; CF=0 ax=007BH; CF=1 ax=00B7H; CF=1

answered Mar 27 in CO & Architecture by Rams B (27 points) | 153 views

+2 votes

1 answer

38

Memory interfacing
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips? (if possible give some reference and diagram)

answered Mar 24 in CO & Architecture by abhishekmehta4u Loyal (9.1k points) | 102 views

+11 votes

3 answers

39

GATE2002-1.24
In the absolute addressing mode the operand is inside the instruction the address of the operand in inside the instruction the register containing the address of the operand is specified inside the instruction the location of the operand is implicit

answered Mar 23 in CO & Architecture by abhishekmehta4u Loyal (9.1k points) | 3.1k views

+1 vote

0 answers

40

Gradeup mocktest
In a pipelined RISC computer, where arithmetic instructions and Load/store instructions are carried out, which of the following method will not definitely help in faster execution when only load/store instruction are performed? a. increasing clock speed b. ... in the program then again forwarding that to the load instruction will increase the speed of the computation. Please guide.

asked Mar 23 in CO & Architecture by V MIDHUN 2 (19 points) | 61 views

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