# Recent questions and answers in CO and Architecture

1
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... are for instruction fetch and $40$% are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________
2
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $\begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\hline \text{MOV$R_1, ... has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$
3
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$
4
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR ... $2$ $3$ $4$ $5$
5
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB ... average instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
6
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$
7
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by $\text{20%}$ and the speed of a fixed point unit has been increased by $\text{10%}$. What is the overall speedup achieved if the ratio of the number of floating point operations ... used to take twice the time taken by the fixed point operation in the original design? $1.155$ $1.185$ $1.255$ $1.285$
8
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
9
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?
10
we do forwarding from WB stage to EX or from WB to MEM stage??
11
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main memory starting from ... of the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
12
An array of $2$ ...
13
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack
1 vote
14
Consider the following instructions. I​ 1​ : R​ 1​ = 100 I​ 2​ : R​ 1​ = R​ 2​ + R​ 4 I​ 3​ : R​ 2​ = R​ 4​ + 25 I​ 4​ : R​ 4​ = R​ 1​ + R​ 3 I​ 5​ : R​ 1​ = R​ 1​ + 30 Calculate sum of (WAR, RAW and WAW) dependencies the above instructions. (a) 10 (c) 6 (b) 12 (d) 8
15
A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?
16
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access ... $10$ times. The number of conflict misses experienced by the cache is _________ .
17
A pipeline processor has two branch delay slots. An optimizing compiler can fill one of these slots 85% of the time and can fill the second slot 20% of the time. What percentage improvement in performence achieved by this optimization, assuming 20% of the instruction executed are branch instruction?
18
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic
19
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following ... is: $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$
20
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 50 cycles. The hit time of L$_2$ cache is 10 cycles. The hit time of the L$_1$ cache is 5 ... 1250 number of cycles with given misses = 1800 stall cycles = 1800-1250 = 550 number of stalls/instruction= 550/200 = 2.75 please verify
1 vote
21
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits
22
Consider the following set of instructions executed by 8085 microprocessor MOV H,20 MOV L,10 MOV E,00 XCHG After the execution, the contents of E register will be ______________ (integer value only). i dont know how to solve this and ques. based on 8085 microprocessor can be asked in GATE??
1 vote
23
Which of the following is correct statement? In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words. The isolated I/O method isolates memory and I/O addresses so that memory ... serial transfer of data the two units share a common clock. In synchronous serial transmission of data the two units have different clocks.
24
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$
25
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... is taken during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$
26
Susheel is setting up a website. He bought a fancy new hard disk which advertises: an 8 ms average seek time. 10000 RPM or roughly 6 ms per rotation. a2 ms overhead for each disk operation. a transfer speed of 10,000,000 bytes per second Susheel had enough ... HTML files have an average size of 8000 bytes. How much time will it take on an average to read a random HTML file from the disk?
27
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ADD and SUB instructions, ... $13$ $15$ $17$ $19$
28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$S _2$} & \textbf {$S _3$} & \textbf{$S _4 ... $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$
29
Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop: for (i = 1; i < = 1000; i++) {I1, I2, I3, I4} where the time taken (in ns) by instructions $I1$ to $I4$ for stages $S1$ to $S4$ ... $I1$ for $i = 2$ will be available after $\text{11 ns}$ $\text{12 ns}$ $\text{13 ns}$ $\text{28 ns}$
30
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. Under ... , and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.
31
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer. ...
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$uses indirect addressing mode.$A$and$B$are memory addresses ... destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is:$3456$1 vote 1 answer 34 Given below are two statements: Statement$I$: Hardwired control unit can be optimized to produce fast mode of operation Statement$II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct answer from the ... are false Statement$I$is correct but Statement$II$is false Statement$I$is incorrect but Statement$II$is true 6 votes 3 answers 35 Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit time in L1 cache is 10 cycles ... number of stall cycles per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance. 0 votes 1 answer 36 Which of the following statements with respect to$K$-segment pipelining are true? Maximum speedup that a pipeline can provide is$k$theoretically It is impossible to achieve maximum speed up$k$in$k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ...$(b)$and$(c)$only$(a)$and$(c)$only$(a), (b)$and$(c)$0 votes 1 answer 37 A non-pipeline system takes$50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of$10$ns. Determine approximately the speedup ratio of the pipeline for$500$tasks.$64.955.75.5$0 votes 1 answer 38 The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ...$1002\text{H}2011\text{H}2022\text{H}0215\text{H}$40 votes 3 answers 39 Consider the following code sequence having five instructions from$I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.$I_1\$: ADD ... of the above statements is/are correct? Only S1 is true Only S2 is true Only S1 and S3 are true Only S2 and S3 are true