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Recent questions and answers in CO and Architecture
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1
GATE CSE 2023 | Question: 32
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip select $\text{(CS)}$ port of these memory blocks through a decoder as shown in the figure. The ... options is $\text{CORRECT}?$ $(0,1,2,3)$ $(0,1024,2048,3072)$ $(0,8,16,24)$ $(0,0,0,0)$
Bhaskar_Saini
answered
in
CO and Architecture
2 days
ago
by
Bhaskar_Saini
1.3k
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gatecse-2023
co-and-architecture
memory-interfacing
2-marks
5
votes
3
answers
2
ISRO2020-46
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes? $1,280,000$ $1280$ $1250$ $128,000$
Bhaskar_Saini
answered
in
CO and Architecture
2 days
ago
by
Bhaskar_Saini
2.4k
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isro-2020
co-and-architecture
disk
normal
1
vote
4
answers
3
GATE CSE 2023 | Question: 54
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.
Bhaskar_Saini
answered
in
CO and Architecture
3 days
ago
by
Bhaskar_Saini
1.1k
views
gatecse-2023
co-and-architecture
cache-memory
numerical-answers
2-marks
2
votes
2
answers
4
GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check for a keystroke and consumes $100\; \mu \mathrm{s}$ (micro seconds) for ... interrupt and processing a keystroke. The ratio $\dfrac{T_{1}}{T_{2}}$ is _____________. (Rounded off to one decimal place)
Bhaskar_Saini
answered
in
CO and Architecture
3 days
ago
by
Bhaskar_Saini
1.6k
views
gatecse-2023
co-and-architecture
interrupts
numerical-answers
1-mark
13
votes
5
answers
5
GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.
Bhaskar_Saini
answered
in
CO and Architecture
3 days
ago
by
Bhaskar_Saini
4.3k
views
gatecse-2022
numerical-answers
co-and-architecture
pipelining
stall
2-marks
2
votes
1
answer
6
co_williams
Let the address stored in the program counter be designated by the symbol X1. The instruction stored in X1 has an address part (operand reference) X2. The operand needed to execute the instruction is stored in the memory word with address X3.An index register contains the ... quantities if the addressing mode of the instruction is (a) direct; (b) indirect; (c) PC relative; (d) indexed?
chandankumar
answered
in
CO and Architecture
Mar 23
by
chandankumar
1.1k
views
4
votes
4
answers
7
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
Abhishek124 Tiwari
answered
in
CO and Architecture
Mar 21
by
Abhishek124 Tiwari
2.0k
views
isro-2020
co-and-architecture
normal
addressing-modes
0
votes
1
answer
8
coa question
Interpret the main memory addresses FF010,12364,andC7691 considering direct, associative and 2 way set associative mapping if the main memory size is 1MB,word size is 16 bytes, and cache size is 64KB.
Bharat Bhushan
answered
in
CO and Architecture
Mar 12
by
Bharat Bhushan
91
views
co-and-architecture
memory-management
2
votes
1
answer
9
Booth's coding in 8-bits for the decimal number -57 is: A 0-100+1000 B 0-100+100-1 C 0-1+100-10+1 D 00-10+100-1
Bharat Bhushan
answered
in
CO and Architecture
Mar 10
by
Bharat Bhushan
768
views
co-and-architecture
booths-algorithm
2
votes
2
answers
10
UGC NET CSE | December 2015 | Part 3 | Question: 6
A CPU handles interrupt by executing interrput service subroutine ____ by checking interrupt register after execution of each instruction by checking interrupt register at the end of the fetch cycle whenever an interrupt is registered by checking interrupt register at regular time interval
Bharat Bhushan
answered
in
CO and Architecture
Mar 9
by
Bharat Bhushan
859
views
ugcnetcse-dec2015-paper3
interrupts
co-and-architecture
3
votes
4
answers
11
UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
Bharat Bhushan
answered
in
CO and Architecture
Mar 9
by
Bharat Bhushan
7.5k
views
ugcnetcse-dec2015-paper3
8086
assembly
co-and-architecture
non-gate
0
votes
2
answers
12
ISRO 2015- Main memory [EE]
Techniques that automatically move program and data blocks into physical main memory when they are required for execution are called (a) Main memory techniques (b) Cache memory techniques (c) Virtual memory techniques (d) Associate memory techniques
Bharat Bhushan
answered
in
CO and Architecture
Mar 9
by
Bharat Bhushan
973
views
isro-ee
co-and-architecture
1
vote
1
answer
13
BARC 2015
Operand is fetched from memory During (A) fetch phase (B) execute phase (C) decode phase (D) read phase
Bharat Bhushan
answered
in
CO and Architecture
Mar 9
by
Bharat Bhushan
78
views
co-and-architecture
0
votes
1
answer
14
self doubt
Can Interrupt-Driven I/O be memory mapped? Polling is memory mapped or IO mapped?
Bharat Bhushan
answered
in
CO and Architecture
Mar 8
by
Bharat Bhushan
61
views
co-and-architecture
io-handling
1
vote
1
answer
15
pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)
Bharat Bhushan
answered
in
CO and Architecture
Mar 6
by
Bharat Bhushan
75
views
pipelining
0
votes
0
answers
16
pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)
closed
Veeresh Badiger
asked
in
CO and Architecture
Mar 5
by
Veeresh Badiger
48
views
pipelining
0
votes
1
answer
17
https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial
In this question can someone plz explain to me the write back part? Why are we taking write back time only for cache misses? Why not for hits? How to know when a block is going to be replaced and when to consider write back time.
Bharat Bhushan
answered
in
CO and Architecture
Mar 5
by
Bharat Bhushan
479
views
cache-memory
co-and-architecture
write-through
0
votes
3
answers
18
Appllied Gate Test Series
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for read, hit ratio of 0.9 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?
Bharat Bhushan
answered
in
CO and Architecture
Mar 5
by
Bharat Bhushan
363
views
co-and-architecture
cache-memory
write-through
0
votes
1
answer
19
homework
Main disadvantage of direct mapping is that cache his ratio decreases sharply it two or more frequently used blocks map on to same region. For two level memory hierarchy cache and main memory, WRITE THROUGH results in more write cycles to main emeory then WRITE BACK. is it true or false ? with reasons ? thank you in advance
Bharat Bhushan
answered
in
CO and Architecture
Mar 5
by
Bharat Bhushan
231
views
co-and-architecture
cache-memory
write-through
true-false
0
votes
1
answer
20
self doubt
true/ false cpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)
Bharat Bhushan
answered
in
CO and Architecture
Mar 5
by
Bharat Bhushan
57
views
co-and-architecture
logical-reasoning
true-false
0
votes
1
answer
21
With the help of the following information, determine the size of the sub-fields (in bits) in the address for direct mapping, associative mapping and set-associative mapping: 512 MB main memory and 2 MB cache memory Address space of the processor is 256 MB The block size is 256 bytes There are 16 blocks in a cache set.
Bharat Bhushan
answered
in
CO and Architecture
Mar 4
by
Bharat Bhushan
126
views
co-and-architecture
0
votes
1
answer
22
ACE Test-4(GCO-2)
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/ ... I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.
Gate Shark
answered
in
CO and Architecture
Mar 4
by
Gate Shark
468
views
co-and-architecture
io-organization
io-handling
2
votes
3
answers
23
GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third stages, respectively. Assume that there is no other ... instruction is fetched every cycle. The total execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$
Hira Thakur
answered
in
CO and Architecture
Feb 16
by
Hira Thakur
1.1k
views
gatecse-2023
co-and-architecture
pipelining
numerical-answers
1-mark
2
votes
1
answer
24
GATE CSE 2023 | Question: 35
Consider the $\textsf{IEEE-754}$ single precision floating point numbers $\text{P} = \textsf{0xC1800000}$ and $\text{Q} = \textsf{0x3F5C2EF4}.$ ... $\textsf{IEEE-754}$ single precision format? $\textsf{0x404C2EF4}$ $\textsf{0x405C2EF4}$ $\textsf{0xC15C2EF4}$ $\textsf{0xC14C2EF4}$
Abdul Kadir 3
answered
in
CO and Architecture
Feb 15
by
Abdul Kadir 3
970
views
gatecse-2023
co-and-architecture
ieee-representation
2-marks
1
vote
1
answer
25
GATE CSE 2023 | Question: 31
Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. Which one of ... $(3,4,4, \text{L01)}$ $(8,1,1, \text{L02)}$ $(3,1,1, \text{L01)}$
akshaw
answered
in
CO and Architecture
Feb 15
by
akshaw
1.1k
views
gatecse-2023
co-and-architecture
assembly-code
2-marks
0
votes
0
answers
26
Relative Addressing Mode
Consider 3-word long jump instruction designed with PC-relative addressing mode, stored in the memory with a starting address of (2000)$_{10}$. Address field of an instruction contains (4000)$_{10}.$ Which of the following statements are true in the instruction ... where operand is stored, then how we can we assign it to PC? PC should be 2003 at the end of execution right?
Chaitanya Kale
asked
in
CO and Architecture
Feb 13
by
Chaitanya Kale
99
views
addressing-modes
co-and-architecture
made-easy-test-series
0
votes
0
answers
27
gate cs 2023
Do any one remember that COA question asked in gate cs 2023 where they have given some code and the options were like a) 3,1,1,L01 b)3,4,4,L01?
gaddalakonda_ganesh
asked
in
CO and Architecture
Feb 11
by
gaddalakonda_ganesh
109
views
co-and-architecture
query
0
votes
1
answer
28
control signal
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
Mr.Gaurav
answered
in
CO and Architecture
Feb 2
by
Mr.Gaurav
80
views
co-and-architecture
control-unit
0
votes
1
answer
29
Unacademy Practice Question
Consider a 4 way set associative cache of size 16 KB organized into 4 words block. Cache memory is designed with the write back protocol having the miss ratio of read and write operations as 30% and 40% respectively. The tine taken by ... 50% read requests and 50% write requests. What is the average memory access time considering both read and write operations ?
Sunnidhya Roy
answered
in
CO and Architecture
Feb 1
by
Sunnidhya Roy
207
views
machine-instructions
co-and-architecture
3
votes
0
answers
30
DMA stealing mode, where does extra 40ns come from?
Consider a disk with 4000 RPM rotational speed. The disk has 1K sectors on each track with 1k capacity of each sector. The disk is operating on the cycle stealing mode of DMA. It takes 50 nsec to transfer the 16 B data from disk to ... to DMA? This is the question here is the solution Can you tell where the 40ns which I have circled comes from??
h4kr
asked
in
CO and Architecture
Jan 31
by
h4kr
106
views
co-and-architecture
0
votes
1
answer
31
Computer Organization and Architecture
Consider two cache organization which are byte addressable.In both cache organization cache size is 64 KB with 32-byte block.The first cache organization is direct mapped while the other is 4-way set associative.Physical address is of size ... latency of OR gate is 1 is.Find sum the latency of the direct mapped organization and set associative organization?
Pranavpurkar
answered
in
CO and Architecture
Jan 31
by
Pranavpurkar
81
views
co-and-architecture
computer-architecture
0
votes
1
answer
32
Operand forwarding Made Easy Question
Consider 4-stage (IF, ID, EX, WB) pipeline used to execute the following code. All instructions are spending are spending one cycle on all the stages but ALU instructions are spending 3 cycles on 3rd stage. I1: LOAD R0, ... Number of cycles are saved using operand forwarding over without operand forwarding is? Can someone please explain by drawing the diagram?
DebRC
answered
in
CO and Architecture
Jan 30
by
DebRC
195
views
pipelining
co-and-architecture
operand-forwarding
made-easy-test-series
0
votes
1
answer
33
Applied Gate Test Series
supreetshukla
answered
in
CO and Architecture
Jan 25
by
supreetshukla
178
views
pipelining
computer-architecture
0
votes
0
answers
34
COA
Which of the following is/are true for a CPU which does not have any stack pointer registers? A Interrupts are not possible. B All subroutine calls and interrupts are possible. C It cannot have nested subroutines call. D It cannot have subroutine call instruction.
Overflow04
asked
in
CO and Architecture
Jan 25
by
Overflow04
120
views
co-and-architecture
self-doubt
interrupts
0
votes
1
answer
35
Practice Question Unacademy - Vishvadeep Gothi
Consider a system which supports 2-address, 1-address and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address instructions and 'y' 1-address instructions then which of the following is the maximum number of 0-address instructions ... $2 ^ i - 2 ^ a * x - y * 2 ^ a$
gatecse
answered
in
CO and Architecture
Jan 23
by
gatecse
112
views
co-and-architecture
machine-instructions
0
votes
3
answers
36
Arihant Gate Tutor
Memory mapping table is used to (a) Translate virtual address to physical address (b) Translate physical address to virtual address (c) Both (d) None
Vasudevarnabmessi
answered
in
CO and Architecture
Jan 22
by
Vasudevarnabmessi
106
views
operating-system
co-and-architecture
virtual-memory
1
vote
0
answers
37
NPTEL Assignment
Question : i. CISC architecture a. Symmetric registers ii. RISC architecture b. Multiple memory references iii. Misalignment c. Condition code register iv. Static data d. Single memory reference Options: i-a,ii-c,iii-b,iv-d i-c,ii-a,iii-b,iv-d i-c,ii-a,iii-b,iv-b i-c,ii-a,iii-d,iv-b
lalitver10
asked
in
CO and Architecture
Jan 12
by
lalitver10
75
views
nptel-quiz
co-and-architecture
0
votes
0
answers
38
Gate 2015
For problems where the options are not given, like this kinda questions should I consider hierarchical access or simultaneous access. I know that hierarchical access is commonly used so it should be preferred but the solution for this is described using simultaneous access.
DAWID15
asked
in
CO and Architecture
Jan 3
by
DAWID15
77
views
virtual-memory
numerical-answers
0
votes
1
answer
39
#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
iamsubhrajit
asked
in
CO and Architecture
Dec 31, 2022
by
iamsubhrajit
136
views
co-and-architecture
cache-memory
0
votes
1
answer
40
Addressing Modes
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (knowing that MOV works only between registers).
Aaryan_Sharma
asked
in
CO and Architecture
Dec 30, 2022
by
Aaryan_Sharma
123
views
co-and-architecture
addressing-modes
goclasses
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Please upload updated previous year question...
The last hardcopy that was made was for GATE 2022...
overall only 3 post .no post for gen male
for gen GS in the range of 720-750 approx.
can we get 2023 hark copy from amazon?