Recent questions and answers in CO & Architecture

0 votes

0 answers

1

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked 3 days ago in CO & Architecture by srestha Veteran (111k points) | 14 views

0 votes

1 answer

2

which book should i refer to cover all the concept of cache memory and memory hierarchy in CO and Architecture.

answered 3 days ago in CO & Architecture by rajabhardwajrai (15 points) | 59 views

0 votes

0 answers

3

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked 4 days ago in CO & Architecture by Ritabrata Dey (35 points) | 16 views

0 votes

0 answers

4

Goldman Sachs Screening Test
In Matrix Multiplication Operation Code uses Temporal Locality and Data uses Spatial Locality Data uses Temporal Locality and Code uses Spatial Locality Both data and code uses Spatial Locality Both data and code uses Temporal Locality

asked Apr 14 in CO & Architecture by ved (9 points) | 9 views

0 votes

0 answers

5

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12 in CO & Architecture by Miny (149 points) | 5 views

+14 votes

3 answers

6

GATE2015-2-24
Assume that for a certain processor, a read request takes $50$ $nanoseconds$ on a cache miss and $5$ $nanoseconds$ on a cache hit. Suppose while running a program, it was observed that $80$% of the processor's read requests result in a cache hit. The average read access time in nanoseconds is _____.

answered Apr 9 in CO & Architecture by Rishi yadav Boss (10.9k points) | 3.5k views

+24 votes

4 answers

7

GATE2008-IT-38
Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address ... back to the stack. ADD (X)−, (X) ADD (X), (X)− ADD −(X), (X)+ ADD −(X), (X)

answered Apr 7 in CO & Architecture by Divy Kala Junior (623 points) | 2.7k views

+28 votes

5 answers

8

GATE2008-72
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; /* ... elements have the same cache index as $ARR[0][0]$? $ARR[0][4]$ $ARR[4][0]$ $ARR[0][5]$ $ARR[5][0]$

answered Apr 5 in CO & Architecture by Piyush #### (77 points) | 3.1k views

+1 vote

3 answers

9

Madeeasy Test Series
Suppose that in 1000 memory references there are 150 misses in first level and 100 misses in second level cache. Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles. If there are 4 memory references per instruction, the average stall per instruction is

answered Apr 5 in CO & Architecture by Sahil Arora (27 points) | 660 views

+2 votes

1 answer

10

average memory access time
The access time of cache memory is 45 nsec and that of main memory is 750 nsec. It is found that 75% of memory requests are for read and remaining for write. If the hit access for read is 0.9 and hit ratio for write is 1 and write through protocol is used, then the average memory access time is ________.

answered Apr 2 in CO & Architecture by Hiral Rajgor (17 points) | 354 views

+1 vote

6 answers

11

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

answered Apr 2 in CO & Architecture by Àbhíjèét Míshrà (47 points) | 3.1k views

0 votes

0 answers

12

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2 in CO & Architecture by srestha Veteran (111k points) | 35 views

0 votes

1 answer

13

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

answered Apr 1 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 58 views

+2 votes

2 answers

14

MadeEasy Subject Test 2019: CO & Architecture - Pipelining
Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?

answered Mar 30 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 393 views

+1 vote

1 answer

15

Allen Career Institute:Computer Organization -Memory
The size of instruction in a single accumulator CPU organization is $16$ bits. In order to evaluate the expressions given below. How much memory space (bytes) is required for storing the program? evaluate the expression from left to right). Expression : $y=\frac{A-B+C}{E+F}$

answered Mar 30 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 37 views

+38 votes

4 answers

16

GATE2000-12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. ... and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

answered Mar 23 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 4.4k views

0 votes

0 answers

17

self-doubt
How do we perform 0 – 1 in 2’s complement subtraction using 1-bit register??

asked Mar 21 in CO & Architecture by Doraemon (195 points) | 18 views

0 votes

0 answers

18

CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20 in CO & Architecture by Devshree Dubey Boss (14k points) | 16 views

0 votes

0 answers

19

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18 in CO & Architecture by Doraemon (195 points) | 24 views

0 votes

1 answer

20

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

answered Mar 17 in CO & Architecture by Anuranjan (61 points) | 39 views

0 votes

1 answer

21

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache

answered Mar 17 in CO & Architecture by Anuranjan (61 points) | 31 views

0 votes

0 answers

22

Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)

asked Mar 17 in CO & Architecture by Anuranjan (61 points) | 13 views

0 votes

0 answers

23

Cache Memory and Arrays
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.

asked Mar 16 in CO & Architecture by amitqy Active (1.9k points) | 13 views

0 votes

0 answers

24

Self-doubt
What is actually meant by average access time experienced by processor?

asked Mar 14 in CO & Architecture by Anuranjan (61 points) | 14 views

+1 vote

2 answers

25

Gateforum Test Series: Databases - Indexing
suppose that in a file organization record size(R)=150 bytes , block size (B)=512 bytes. there are totally 30000 records. the data field on which indexing is done is 9 bytes and block pointer size is 7 bytes how many block access will be needed to access a data item in case of single level primary indexing?

answered Mar 14 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 62 views

+1 vote

1 answer

26

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

answered Mar 13 in CO & Architecture by Debdeep1998 Junior (635 points) | 44 views

+1 vote

1 answer

27

Self-doubt
What is meant by cache index? Please state by example.

answered Mar 13 in CO & Architecture by Debdeep1998 Junior (635 points) | 42 views

0 votes

2 answers

28

UGCNET-DEC2018-II-16
The decimal floating point number $-40.1$ represented using $IEEE-754 \: 32$-bit representation and written in hexadecimal form is $0xC2206666$ $0xC2206000$ $0xC2006666$ $0xC200600$

answered Mar 13 in Others by abhishekmehta4u Boss (33.4k points) | 95 views

0 votes

1 answer

29

NTA NET DEC 2018

answered Mar 13 in CO & Architecture by Debdeep1998 Junior (635 points) | 38 views

0 votes

0 answers

30

selfdoubt
Show how to do the following statement c = a[2] + b[0] a) using register direct, imm, register indirect b) using register direct, imm, absolute addressing c) using register direct, imm, register indirect with displacement

asked Mar 13 in CO & Architecture by manisha11 Active (2k points) | 41 views

+1 vote

3 answers

31

Testbook Test Series: CO & Architecture - Addressing Modes

answered Mar 11 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 256 views

0 votes

0 answers

32

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles). [closed]

asked Mar 10 in CO & Architecture by s_dr_13 (133 points) | 42 views

+1 vote

1 answer

33

Self-doubt
What does tag number signifies in line in cache?

answered Mar 10 in CO & Architecture by Debdeep1998 Junior (635 points) | 25 views

0 votes

3 answers

34

self doubt
How to do:(1000)base3 – (121)base3 without converting them to base 10 the final answer should be in base3

answered Mar 9 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 63 views

+1 vote

0 answers

35

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

asked Mar 8 in CO & Architecture by s_dr_13 (133 points) | 39 views

0 votes

1 answer

36

Delayed Branching
can some one tell me any good resource to study delayed branching in computer architecture ?? Especially numerical examples.

answered Mar 7 in CO & Architecture by amitqy Active (1.9k points) | 116 views

+1 vote

3 answers

37

Ace Test Series: CO & Architecture - Addressing Modes
Given answer is A. I am doubtful between A and B why not B is faster than A. Please explain

answered Mar 6 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 688 views

0 votes

1 answer

38

test series
Consider the following IEEE single precision format A fractional number X is stored as (80700000)16. The decimal equivalent of X is ______.

answered Mar 4 in CO & Architecture by Mak Indus (205 points) | 75 views

0 votes

1 answer

39

UPPCL AE 2018:21

answered Mar 4 in CO & Architecture by saurav raghaw Active (1.4k points) | 81 views

0 votes

2 answers

40

MadeEasy Test Series: CO & Architecture - Instruction Format
How will this question be solved?

answered Mar 3 in CO & Architecture by abhishekmehta4u Boss (33.4k points) | 71 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Recent questions and answers in CO & Architecture

Recent Posts

Recent Blog Comments