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Recent questions and answers in CO and Architecture
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BARC 2024 CSE
How many 256 X 1K bit chips are required to build 1 MB of memory?
mrtejas99
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mrtejas99
43
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easy
co-and-architecture
0
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2
Made Easy Class Question.
Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below. S1 S2 S3 S4 I1 1 3 1 2 I2 1 1 3 1 I3 2 1 1 2 I4 1 1 1 2 (a) How many cycles are required to complete the ... ;= n; i++) { I1; I2; I3; I4; } The output of the instruction "I2" will be available after _____ cycles for I2.
sanjeet24
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by
sanjeet24
78
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pipelining
52
votes
10
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3
GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$
sanjeet24
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Mar 4
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sanjeet24
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1
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1
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4
GATE CSE 2024 | Set 2 | Question: 51
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$ ... the number of bits used to encode the immediate value/address field. The value of $\text{X+2Y+Z}$ is __________.
Suraj7
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Feb 21
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Suraj7
1.5k
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gatecse2024-set2
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0
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0
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5
Gate 2024 CS/IT shift-2 Question 61
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below. ... the number of bits used to encode the immediate value/address field. The value of 𝑋 + 2𝑌 + 𝑍 is ________
closed
Omkar_Naikwadi
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in
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Feb 19
by
Omkar_Naikwadi
162
views
2
votes
1
answer
6
GATE CSE 2024 | Set 2 | Question: 47
A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a $16$-bit scalar field. If $8$ addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ___________.
amanbh123
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Feb 18
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amanbh123
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gatecse2024-set2
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co-and-architecture
2
votes
2
answers
7
GATE CSE 2024 | Set 1 | Question: 20
Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are ... cannot prevent all pipeline stalls Forwarding does not require any extra hardware to retrieve the data from the pipeline stages
Deepak Poonia
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CO and Architecture
Feb 18
by
Deepak Poonia
3.6k
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gatecse2024-set1
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co-and-architecture
1
vote
2
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8
GATE CSE 2024 | Set 1 | Question: 46
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$ miss rate on instruction cache and $8 \%$ miss rate on data ... rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is __________.
Deepak Poonia
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Feb 18
by
Deepak Poonia
2.3k
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gatecse2024-set1
numerical-answers
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0
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2
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9
GATE CSE 2024 | Set 1 | Question: 45
The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time can be fully parallelized. The overhead for using an ... the parallelized code for an equal amount of time. The number of cores that minimize the execution time of the program is __________.
minip
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Feb 17
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minip
1.5k
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gatecse2024-set1
numerical-answers
co-and-architecture
1
vote
2
answers
10
GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy. Both of them use the $\text{LRU}$ (Least Recently Used) block ... write miss in $\text{WTC}$ always writes the victim cache block to main memory before loading the missed block to the cache
Sachin Mittal 1
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CO and Architecture
Feb 17
by
Sachin Mittal 1
1.8k
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gatecse2024-set1
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cache-memory
multiple-selects
1
vote
1
answer
11
GATE CSE 2024 | Set 2 | Question: 1
Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per ... $\text{DMA}$? $2,56,000$ $3,200$ $25,60,000$ $32,000$
JayRathi
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CO and Architecture
Feb 17
by
JayRathi
2.1k
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gatecse2024-set2
co-and-architecture
0
votes
2
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12
GATE CSE 2024 | Set 1 | Question: 5
Which one of the following statements is FALSE? In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle For bulk data transfer, the burst mode of ... driven I/O mechanism The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts
phaniphani
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CO and Architecture
Feb 17
by
phaniphani
1.9k
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gatecse2024-set1
co-and-architecture
1
vote
1
answer
13
GATE CSE 2024 | Set 2 | Question: 21
An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequence of instructions to be executed in a pipelined processor: $\text{I 1: DIV R3, R1, R2}$ ... $\text{I 3}$ There is a WAW dependency on $\text{R 3}$ between $\text{I 3}$ and $\text{I 4}$
Deepak Poonia
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Feb 17
by
Deepak Poonia
1.6k
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gatecse2024-set2
co-and-architecture
multiple-selects
0
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14
#Self doubt COA
Çșȇ ʛấẗẻ
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Feb 17
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Çșȇ ʛấẗẻ
302
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computer
co-and-architecture
2
votes
0
answers
15
GATE CSE 2024 | Set 2 | Question: 48
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is then redesigned to operate on a $5$ ... hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ____________.
Arjun
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Feb 16
by
Arjun
1.4k
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gatecse2024-set2
numerical-answers
co-and-architecture
pipelining
4
votes
1
answer
16
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 55
Consider the cache of size 512 bytes that is direct-mapped? Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data except for the array x are stored in registers, and that the ... ) { sum += x[i]; } What is the miss rate for the above loop? (roundoff to two decimal places)
GO Classes
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Feb 5
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GO Classes
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goclasses2024-mockgate-14
numerical-answers
co-and-architecture
cache-memory
page-fault
2-marks
5
votes
1
answer
17
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 62
At a particular point in time, the buffer cache has dirty data that needs to be flushed to disk. Suppose that the identities of these blocks can be listed in [track:sector] form as follows: ... Shortest Seek Time First Scan (initially moving upwards) Look (initially moving upwards) C-SCAN (initially moving upwards)
GO Classes
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in
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Feb 5
by
GO Classes
372
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goclasses2024-mockgate-14
co-and-architecture
disk-scheduling
multiple-selects
2-marks
11
votes
1
answer
18
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 63
Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are taken. We have a 4-stage pipeline where branch target locations ... $1.38$ For both "predict taken", "predict not taken" branch predictions, CPI is the $1.30$
GO Classes
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in
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Feb 5
by
GO Classes
683
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goclasses2024-mockgate-14
co-and-architecture
branch-conditional-instructions
2-marks
7
votes
3
answers
19
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 48
Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, $6$ bits are used to encode one register number, $6$ bits ... $4$ bytes long. How many instructions away (the number of instructions) from the $\textsf{BEQ}$ instruction could we reach?
Kushagrakk
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Feb 4
by
Kushagrakk
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goclasses2024-mockgate-12
goclasses
numerical-answers
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2-marks
0
votes
0
answers
20
#pipeline#coa#mocktest
Mohanasainarala
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Feb 4
by
Mohanasainarala
81
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25
votes
4
answers
21
GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.
ajayraho
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CO and Architecture
Jan 31
by
ajayraho
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gatecse-2020
numerical-answers
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pipelining
2-marks
9
votes
2
answers
22
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 53
Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$ $\textsf{0x80000004}$ $\textsf{0x80000008}$ $\textsf{0x80000010}$ $\textsf{0x80000002}$
Sachin Mittal 1
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CO and Architecture
Jan 29
by
Sachin Mittal 1
699
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goclasses2024-mockgate-13
goclasses
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ieee-representation
2-marks
64
votes
3
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23
GATE CSE 2008 | Question: 76
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction
Deepak Poonia
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CO and Architecture
Jan 29
by
Deepak Poonia
17.8k
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gatecse-2008
co-and-architecture
pipelining
normal
7
votes
1
answer
24
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 35
Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in which $30 \%$ of the instructions are ... is always started and ignored if the branch is taken. What is the throughput (Million instructions per second) of the system?
Aparichit0
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CO and Architecture
Jan 29
by
Aparichit0
613
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goclasses2024-mockgate-13
goclasses
co-and-architecture
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numerical-answers
1-mark
2
votes
1
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25
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 34
In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false? Instruction immediately following the branch condition Instruction immediately preceding the branch condition Instruction that belongs to a different a subroutine It waits till the branch condition is evaluated
GO Classes
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CO and Architecture
Jan 28
by
GO Classes
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goclasses2024-mockgate-13
goclasses
co-and-architecture
branch-conditional-instructions
1-mark
6
votes
1
answer
26
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 54
Assume a cache memory with the following properties: The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes) The cache uses an LRU (least recently used) policy for eviction. The cache is initially empty. Suppose that for the following ... cache? $\text{B}=4$ bytes $\text{B}=8$ bytes $\text{B}=16$ bytes None of the above.
GO Classes
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CO and Architecture
Jan 28
by
GO Classes
675
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goclasses2024-mockgate-13
goclasses
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cache-memory
2-marks
4
votes
1
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27
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 58
Your code is required to perform the function $(\text{M}\%16) \ast 3.$ What should you do to eliminate multiplication ($\ast$) and mod($\%$), assuming $\mathrm{M}$ is $32$ bits wide? shift $\text{M}$ right by $4,$ ... $0000000 \mathrm{Fh}$, save the result, shift result left by $2,$ and add the saved result to current result.
GO Classes
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Jan 28
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GO Classes
367
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goclasses2024-mockgate-13
goclasses
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2-marks
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3
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28
MADE EASY TEST SERIES 2024 #COA
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ADD operation with Address 1 used as Source1 and Destination, Address2 used ... operation consumes 4 cycles. Memory reference consumes 6 cycles. Time required to complete the instruction is in (ns).
vedantk
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CO and Architecture
Jan 27
by
vedantk
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3
votes
2
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29
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 5
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresses. How many bits will be used for the index?
prasantkr.singh
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in
CO and Architecture
Jan 23
by
prasantkr.singh
463
views
goclasses2024-mockgate-12
goclasses
numerical-answers
co-and-architecture
cache-memory
1-mark
6
votes
1
answer
30
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 20
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI on machine $\text{A}$ is $1.2.$ For the same program, the average ... Machine $\text{B}$, with respect to this program. What is $\mathrm{K}?$ $1$ $4 / 3$ $2$ $3 / 4$
GO Classes
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CO and Architecture
Jan 21
by
GO Classes
572
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goclasses2024-mockgate-12
goclasses
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machine-instruction
1-mark
7
votes
1
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31
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 49
Consider the following code fragment: Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true data dependencies be $\mathrm{X}$ ... output dependencies be $\text{Z}$. What is $\mathrm{X}+2 \mathrm{Y}+3 \mathrm{Z}?$
GO Classes
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in
CO and Architecture
Jan 21
by
GO Classes
906
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goclasses2024-mockgate-12
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numerical-answers
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2-marks
8
votes
1
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32
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits. Which of the following address pairs can be placed in the cache simultaneously? $\textsf{3AC6 F45 6}$ ... $\textsf{5E3C 768 0}$ and $\textsf{8F3C 768 A}$ $\textsf{2233 445 5}$ and $\textsf{2233 445 C}$
GO Classes
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Jan 21
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GO Classes
744
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54
votes
2
answers
33
GATE CSE 2008 | Question: 36
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III
prasantkr.singh
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Jan 19
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prasantkr.singh
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5
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34
Micro programmed Control Unit
Microprogrammed control unit uses fixed logic to interrupt instruction. True or False.
prasantkr.singh
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CO and Architecture
Jan 17
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prasantkr.singh
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microprogramming
control-unit
0
votes
1
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35
Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be active anytime. The micro instruction of the control unit stores control signal information along with 3-bit MUX select and 12 bits address field. The size of the control memory required is?
prasantkr.singh
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CO and Architecture
Jan 17
by
prasantkr.singh
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co-and-architecture
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microprogramming
0
votes
1
answer
36
computer architecture
a computer has 32-bit instructions and 12-bit addressing if there are already 250 two address instruction how many one address instruction can be formulated
Mrityudoot
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in
CO and Architecture
Jan 16
by
Mrityudoot
139
views
co-and-architecture
0
votes
2
answers
37
Classic RISC Pipeline
In which stage of the classic RISC pipeline, operand is fetched. Is it in Instruction Decode or Execute (ALU) stage?
Shalini_18
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in
CO and Architecture
Jan 16
by
Shalini_18
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pipelining
5
votes
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answer
38
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 34
Which of the following is the best justification for using the middle bits of an address as the set index into a cache rather than the most significant bits? Indexing with the most significant bits would necessitate a smaller ... is likely to make more efficient use of the cache with middle-bit indexing than with high-bit indexing.
amitarp818
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CO and Architecture
Jan 15
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amitarp818
385
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goclasses2024-mockgate-11
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0
votes
1
answer
39
Ace Test Series | Computer Organistaion
A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were no hazards. It is used with copy- back data cache with a block size of one - ... store which only result hazards. What is the throughout of CPU. a) 31 MIPS b) 24 MIPS c) 48 MIPS d) 10 MIPS
p007
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CO and Architecture
Jan 14
by
p007
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ace-test-series
computer-architecture
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throughput
2
votes
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40
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 42
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $\textsf{RAMs}\: 1, 2, 3$ and $4$ ... $\textsf{0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH}$
SankarVinayak
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CO and Architecture
Jan 14
by
SankarVinayak
386
views
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