GATE Overflow for GATE CSE - Recent questions tagged digital-logic
https://gateoverflow.in/tag/digital-logic
Powered by Question2AnswerKMaps - Digital Logic (self doubt)
https://gateoverflow.in/389078/kmaps-digital-logic-self-doubt
<p>I’m taking for an example kmaps for 3 var</p>
<p> </p>
<table border="1" cellpadding="1" style="height:50px; width:293px">
<tbody>
<tr>
<td> </td>
<td>A’B’</td>
<td>A’B</td>
<td>AB</td>
<td>AB’</td>
</tr>
<tr>
<td>C’</td>
<td> 0</td>
<td>1</td>
<td>3</td>
<td>2</td>
</tr>
<tr>
<td style="height:1px">C</td>
<td style="height:1px">4</td>
<td style="height:1px">5</td>
<td style="height:1px">7</td>
<td style="height:1px">6</td>
</tr>
</tbody>
</table>
<p>(probably here we are taking CAB’ = 6</p>
<p>and below like AB’C =5 )</p>
<p> </p>
<table border="1" cellpadding="1" style="height:50px; width:293px">
<tbody>
<tr>
<td> </td>
<td>A’B’</td>
<td>A’B</td>
<td>AB</td>
<td>AB’</td>
</tr>
<tr>
<td>C’</td>
<td> 0</td>
<td>2</td>
<td>6</td>
<td>4</td>
</tr>
<tr>
<td style="height:1px">C</td>
<td style="height:1px">1</td>
<td style="height:1px">3</td>
<td style="height:1px">7</td>
<td style="height:1px">5</td>
</tr>
</tbody>
</table>
<p> </p>
<p><strong>But how do i know which one to use and when? </strong><br>
</p>Digital Logichttps://gateoverflow.in/389078/kmaps-digital-logic-self-doubtMon, 21 Nov 2022 16:22:06 +0000Self doubts
https://gateoverflow.in/388016/self-doubts
Minimal SOP and POS forms are always Identical.<br />
true or false?Digital Logichttps://gateoverflow.in/388016/self-doubtsWed, 09 Nov 2022 09:01:36 +0000Telegram Quiz
https://gateoverflow.in/387916/telegram-quiz
(1101)x = (241)16<br />
<br />
x = ?Digital Logichttps://gateoverflow.in/387916/telegram-quizTue, 08 Nov 2022 03:58:09 +0000How many m-input NAND gates will be required to construct a n-input NAND gate, where (m <= n)?
https://gateoverflow.in/387897/many-input-nand-gates-will-required-construct-input-gate-where
How many $m-$ input NAND gates are needed to construct a $n-$ input NAND gate, where $m \leq n$<br />
<br />
<br />
<br />
Examples:<br />
<br />
> constructing $3-$input NAND gate using $2-$input NAND gate<br />
<br />
> constructing $4-$input NAND gate using $2-$input NAND gate<br />
<br />
> constructing $4-$input NAND gate using $4-$input NAND gate<br />
<br />
<br />
<br />
Is there a general solution to this problem, or is there NO general solution available (i.e., a localized solution may exist)?Digital Logichttps://gateoverflow.in/387897/many-input-nand-gates-will-required-construct-input-gate-whereMon, 07 Nov 2022 20:04:00 +0000MadeEasy Workbook | MUX
https://gateoverflow.in/387311/madeeasy-workbook-mux
<p><img alt="" src="https://gateoverflow.in/?qa=blob&qa_blobid=16094989722906700587"></p>Digital Logichttps://gateoverflow.in/387311/madeeasy-workbook-muxThu, 03 Nov 2022 05:47:04 +0000DIGITAL LOGIC | MUX conversion | MadeEasy Workbook question
https://gateoverflow.in/387309/digital-logic-mux-conversion-madeeasy-workbook-question
<p><img alt="" src="https://gateoverflow.in/?qa=blob&qa_blobid=4815511097582328926"></p>Digital Logichttps://gateoverflow.in/387309/digital-logic-mux-conversion-madeeasy-workbook-questionThu, 03 Nov 2022 05:41:56 +0000Digital Logic | 2's complement Question | MadeEasy Workbook question
https://gateoverflow.in/386257/digital-logic-complement-question-madeeasy-workbook-question
<p><img alt="" src="https://gateoverflow.in/?qa=blob&qa_blobid=9775411958561476159"></p>Digital Logichttps://gateoverflow.in/386257/digital-logic-complement-question-madeeasy-workbook-questionMon, 24 Oct 2022 11:26:29 +0000The number of address lines required to address 8 GB memory is a) 8 b) 1024 c) 32 d) 33 . Please help
https://gateoverflow.in/385037/number-address-lines-required-address-memory-1024-please-help
CO and Architecturehttps://gateoverflow.in/385037/number-address-lines-required-address-memory-1024-please-helpTue, 11 Oct 2022 10:11:59 +0000Digital Logic Question
https://gateoverflow.in/384685/digital-logic-question
<p><img alt="" src="https://gateoverflow.in/?qa=blob&qa_blobid=3994240004887310315"></p>Digital Logichttps://gateoverflow.in/384685/digital-logic-questionFri, 07 Oct 2022 08:29:10 +0000Digital Logic Question
https://gateoverflow.in/384682/digital-logic-question
Consider the following statements regarding the logic circuits:<br />
<br />
1. In combinational logic circuits, the outputs at any instant of time are entirely dependent upon the inputs present at that time.<br />
<br />
2. The behavior of synchronous sequential circuit depends upon the order in which its input signals change and can be affected at any instant of time.<br />
<br />
3. Synchronous sequential circuits that use clock pulses in the inputs of memory elements are called clocked sequential circuits.<br />
<br />
Which of the above statements are correct?<br />
<br />
(a) 1, 2 and 3<br />
<br />
(b) 1 and 2 only<br />
<br />
(c) 2 and 3 only<br />
<br />
(d) 1 and 3 onlyDigital Logichttps://gateoverflow.in/384682/digital-logic-questionFri, 07 Oct 2022 08:26:32 +0000Digital Logic
https://gateoverflow.in/383424/digital-logic
To design n input NOR gate, the number of 2 input NOR gate =2n - 3.<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
Somebody please verify and explain with example ( diagram).Digital Logichttps://gateoverflow.in/383424/digital-logicThu, 22 Sep 2022 04:12:52 +0000Digital Logic | Doubt
https://gateoverflow.in/383140/digital-logic-doubt
Hamming Distance: We can calculate how much Hamming Distance should be there so that we can correct any wrong bit<br />
<br />
Hamming Code: By Hamming Code we can correct any wrong bit.<br />
<br />
Questions:<br />
<br />
1] Are they both different techniques or there is relation between Hamming Distance and Hamming Code?<br />
or Hamming Distance is a generic concept(we can calculate Hamming Distance in any two numbers).<br />
<br />
2] Why should anybody use Hamming Code where we can correct error by Hamming Distance?Digital Logichttps://gateoverflow.in/383140/digital-logic-doubtSun, 18 Sep 2022 13:30:12 +0000Applied test series question
https://gateoverflow.in/382873/applied-test-series-question
<p><strong>A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs are made available in both complemented and uncomplemented form and carry network has been implemented using AND, Or gates.</strong></p>
<p><strong>can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?</strong></p>Digital Logichttps://gateoverflow.in/382873/applied-test-series-questionTue, 13 Sep 2022 21:02:19 +0000Computer architecture
https://gateoverflow.in/382686/computer-architecture
Represent +42 and -42 in sign-magnitude, 1’s complement and 2’s complement<br />
<br />
representation. Find the result of 42 - 20 using 2’s complement.Digital Logichttps://gateoverflow.in/382686/computer-architectureSun, 11 Sep 2022 09:16:36 +0000Number representation
https://gateoverflow.in/382114/number-representation
<p>Does the formula(2^(k-1)) used for caculating the biasing value is correct?<img alt="" src="https://gateoverflow.in/?qa=blob&qa_blobid=3360593472145706348"></p>
<p> </p>
<p> </p>
<p><img alt="" src="https://gateoverflow.in/?qa=blob&qa_blobid=7499787233718790318"></p>Digital Logichttps://gateoverflow.in/382114/number-representationSat, 03 Sep 2022 07:29:20 +0000Computer Architecture and Organisation
https://gateoverflow.in/381968/computer-architecture-and-organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So:<br />
a) How many multiplexer is needed?<br />
b) What type of multiplexer is required i.e size of multiplexer?<br />
c) Describe decoder used to select address of memory unitCO and Architecturehttps://gateoverflow.in/381968/computer-architecture-and-organisationThu, 01 Sep 2022 13:24:21 +0000#gate #digital logic #neutral function #derivation
https://gateoverflow.in/381254/%23gate-%23digital-logic-%23neutral-function-%23derivation
How formula of neutral function is derived? I get that it has equal number of max and min terms but didnt get derivationDigital Logichttps://gateoverflow.in/381254/%23gate-%23digital-logic-%23neutral-function-%23derivationWed, 24 Aug 2022 09:08:28 +0000Made easy 2022 Test Series
https://gateoverflow.in/380226/made-easy-2022-test-series
<p><img alt="" height="122" src="https://gateoverflow.in/?qa=blob&qa_blobid=3773763122367410911" width="930"></p>
<p>Please Explain How to Solve this type question in detail if any source Please share.</p>Digital Logichttps://gateoverflow.in/380226/made-easy-2022-test-seriesTue, 09 Aug 2022 16:15:25 +0000ISI2020-PCB-CS: 8.1
https://gateoverflow.in/380060/isi2020-pcb-cs-8-1
Simplify the following Boolean function in product-of-sums form: $$ F(A, B, C, D)=\sum(0,1,2,5,8,9,10) . $$Digital Logichttps://gateoverflow.in/380060/isi2020-pcb-cs-8-1Mon, 08 Aug 2022 17:51:44 +0000ISI2020-PCB-CS: 10
https://gateoverflow.in/380058/isi2020-pcb-cs-10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explain how these two decoders can be used to access the memory of size $2^{n}$.<br />
<br />
Determine the value of $k$ that achieves minimum address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.Digital Logichttps://gateoverflow.in/380058/isi2020-pcb-cs-10Mon, 08 Aug 2022 17:51:44 +0000Digital Logic - Gray Code Representation
https://gateoverflow.in/379579/digital-logic-gray-code-representation
Hi,<br />
<br />
Can someone please tell if gray code representation can also work for negative binary number?<br />
<br />
I’ve seen examples of gray code for only positive binary number not sure about negative , can someone pls clear the doubt ?Digital Logichttps://gateoverflow.in/379579/digital-logic-gray-code-representationMon, 01 Aug 2022 16:42:20 +0000