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Most viewed questions

63 votes
3 answers
1
Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
asked Dec 18, 2015 in Digital Logic bahirNaik 66.2k views
9 votes
3 answers
2
relation
Number of relations $S$ over set $\{0,1,2,3 \}$ such that $(x,y) \in S \Rightarrow x = y$
Number of relations $S$ over set $\{0,1,2,3 \}$ such that $(x,y) \in S \Rightarrow x = y$
asked Dec 27, 2017 in Set Theory & Algebra Lakshman Patel RJIT 43.1k views
174 votes
11 answers
3
GATE2008-67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows: ... page tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ ... level page tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
asked Sep 12, 2014 in Operating System Kathleen 42k views
20 votes
1 answer
4
gate rank prediction
Hi i just want to ask if i am scoring 40 to 45% marks in made easy FLT s and my rank is near about 200 -250 where 1000 students have appeared what could be my gate rank as per previous year student experiences? a silly q though but i wnt to know!
Hi i just want to ask if i am scoring 40 to 45% marks in made easy FLT s and my rank is near about 200 -250 where 1000 students have appeared what could be my gate rank as per previous year student experiences? a silly q though but i wnt to know!
asked Jan 17, 2016 in Others Aboveallplayer 40.9k views
91 votes
16 answers
6
GATE2017-2-44
Two transactions $T_1$ and $T_2$ are given as $T_1:r_1(X)w_1(X)r_1(Y)w_1(Y)$ $T_2:r_2(Y)w_2(Y)r_2(Z)w_2(Z)$ where $r_i(V)$ denotes a $\textit{read}$ operation by transaction $T_i$ on a variable $V$ and $w_i(V)$ denotes a $\textit{write}$ operation by transaction $T_i$ on a variable $V$. The total number of conflict serializable schedules that can be formed by $T_1$ and $T_2$ is ______
Two transactions $T_1$ and $T_2$ are given as $T_1:r_1(X)w_1(X)r_1(Y)w_1(Y)$ $T_2:r_2(Y)w_2(Y)r_2(Z)w_2(Z)$ where $r_i(V)$ denotes a $\textit{read}$ operation by transaction $T_i$ on a variable $V$ and $w_i(V)$ denotes a $\textit{write}$ operation by transaction $T_i$ on a variable $V$. The total number of conflict serializable schedules that can be formed by $T_1$ and $T_2$ is ______
asked Feb 14, 2017 in Databases Madhav 36k views
106 votes
16 answers
7
GATE2004-47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The ... instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB ... average instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
asked Sep 5, 2014 in CO and Architecture gatecse 34.3k views
3 votes
1 answer
8
Gate Response Sheet and Marks Calculator GATE 2018
Response sheet has been released for gate 2018. When will the marks calculator be launched?
Response sheet has been released for gate 2018. When will the marks calculator be launched?
asked Feb 14, 2018 in GATE Shubham Kumar Gupta 29.9k views
0 votes
5 answers
9
The maximum number of nodes on level i of a binary tree
Level of a node is distance from root to that node. For example, level of root is 1 and levels of left and right children of root is 2. The maximum number of nodes on level i of a binary tree is In the following answers, the operator '^' indicates power a) 2^i-1 b)2^i c)2^i+1 d)2^(i+1/2)
Level of a node is distance from root to that node. For example, level of root is 1 and levels of left and right children of root is 2. The maximum number of nodes on level i of a binary tree is In the following answers, the operator '^' indicates power a) 2^i-1 b)2^i c)2^i+1 d)2^(i+1/2)
asked Jan 16, 2016 in Algorithms Akanksha Kesarwani 29.7k views
85 votes
17 answers
10
GATE2016-1-8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
asked Feb 12, 2016 in Digital Logic Sandeep Singh 27.6k views
88 votes
17 answers
12
GATE2009-57, ISRO2016-75
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into this link to maximally pack them in transit (within the link). What is the minimum ... distinctly? Assume that no time gap needs to be given between transmission of two frames. $I=2$ $I=3$ $I=4$ $I=5$
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into this link to maximally pack them in transit (within the link). What is the minimum number of bits ... numbers distinctly? Assume that no time gap needs to be given between transmission of two frames. $I=2$ $I=3$ $I=4$ $I=5$
asked Sep 22, 2014 in Computer Networks Kathleen 26.8k views
5 votes
5 answers
13
About Gate 2018 Answer key
Does anyone know exactly when official answer key will be out?
Does anyone know exactly when official answer key will be out?
asked Feb 5, 2018 in GATE Abhijit Howal 26.2k views
112 votes
4 answers
14
GATE2005-68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register ... cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register read ... clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
asked Sep 22, 2014 in CO and Architecture Kathleen 25.8k views
60 votes
15 answers
15
GATE2014-1-39
The minimum number of comparisons required to find the minimum and the maximum of $100$ numbers is ________
The minimum number of comparisons required to find the minimum and the maximum of $100$ numbers is ________
asked Sep 28, 2014 in Algorithms jothee 25.8k views
93 votes
4 answers
16
GATE2001-2.23
$R(A,B,C,D)$ is a relation. Which of the following does not have a lossless join, dependency preserving $BCNF$ decomposition? $A \rightarrow B, B \rightarrow CD$ $A \rightarrow B, B \rightarrow C, C \rightarrow D$ $ AB \rightarrow C, C \rightarrow AD$ $A \rightarrow BCD$
$R(A,B,C,D)$ is a relation. Which of the following does not have a lossless join, dependency preserving $BCNF$ decomposition? $A \rightarrow B, B \rightarrow CD$ $A \rightarrow B, B \rightarrow C, C \rightarrow D$ $ AB \rightarrow C, C \rightarrow AD$ $A \rightarrow BCD$
asked Sep 15, 2014 in Databases Kathleen 25.5k views
80 votes
9 answers
17
GATE2013-45
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... taken during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... is taken during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$
asked Sep 6, 2014 in CO and Architecture Kriss Singh 25.1k views
7 votes
1 answer
18
How to find number of swappings in bubble sort in least possible time ( any shortcut available )
1. The number of swappings needed to sort the numbers: 8, 22, 7, 9, 31, 19, 5, 13 in ascending order using bubble sort is— (a) 11 (b) 12 (c) 13 (d) 14 I know how to solve it using straightforward method. What I did was to write every pass and check the swappings. But , it takes too much time. Is there any shortcut possible ?
asked Aug 2, 2015 in Algorithms worst_engineer 23.5k views
72 votes
11 answers
19
GATE2015-2-48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 ... -carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds ... ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.
asked Feb 13, 2015 in Digital Logic jothee 22.8k views
5 votes
3 answers
20
Difference between DPDA and NPDA?
asked Jun 1, 2016 in Theory of Computation Amit Sharma 22.7k views
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