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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Recent questions in CO and Architecture

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2 answers
1
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack
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The process of entering data into a storage location causes variation in its address number adds to the contents of the location is called a readout operation is destructive of previous contents
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1 answer
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If a processor does not have any stack pointer register, then it cannot have subroutine call instruction it can have subroutine call instruction, but no nested subroutine calls nested subroutine calls are possible, but interrupts are not all sequences of subroutine calls and also interrupts are possible
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1 answer
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1 vote
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19
1 vote
4 answers
20
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