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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Recent questions in CO and Architecture

2 votes
3 answers
1
GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
asked Feb 18 in CO and Architecture Arjun 610 views
2 votes
1 answer
2
GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ ... $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ processor. If $0.5 \%$ processor cycles are used for $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
asked Feb 18 in CO and Architecture Arjun 560 views
1 vote
0 answers
3
GATE CSE 2021 Set 2 | Question: 27
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write ... false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
asked Feb 18 in CO and Architecture Arjun 470 views
5 votes
2 answers
4
GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
asked Feb 18 in CO and Architecture Arjun 734 views
0 votes
3 answers
5
GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
asked Feb 18 in CO and Architecture Arjun 301 views
1 vote
2 answers
6
GATE CSE 2021 Set 1 | Question: 53
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
asked Feb 18 in CO and Architecture Arjun 339 views
0 votes
1 answer
7
GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
asked Feb 18 in CO and Architecture Arjun 377 views
1 vote
1 answer
8
UGCNET-Oct2020-II: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
asked Nov 20, 2020 in CO and Architecture jothee 388 views
0 votes
1 answer
9
UGCNET-Oct2020-II: 6
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$
asked Nov 20, 2020 in CO and Architecture jothee 463 views
0 votes
1 answer
10
UGCNET-Oct2020-II: 7
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
asked Nov 20, 2020 in CO and Architecture jothee 232 views
0 votes
1 answer
11
UGCNET-Oct2020-II: 43
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
asked Nov 20, 2020 in CO and Architecture jothee 171 views
0 votes
0 answers
12
UGCNET-Oct2020-II: 44
Which of the following statements with respect to multiprocessor system are true? Multiprocessor system is controlled by one operating system In Multiprocessor system, multiple computers are connected by the means of communication lines Multiprocessor system is classified as multiple instruction stream and multiple ... $(b)$ only $(a)$ and $(c)$ only $(b)$ and $(c)$ only
Which of the following statements with respect to multiprocessor system are true? Multiprocessor system is controlled by one operating system In Multiprocessor system, multiple computers are connected by the means of communication lines Multiprocessor system is classified as multiple instruction stream and multiple data stream ... $(b)$ only $(a)$ and $(c)$ only $(b)$ and $(c)$ only
asked Nov 20, 2020 in CO and Architecture jothee 107 views
0 votes
2 answers
13
UGCNET-Oct2020-II: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
asked Nov 20, 2020 in CO and Architecture jothee 195 views
1 vote
1 answer
14
UGCNET-Oct2020-II: 81
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct ... false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct answer from the ... are false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true
asked Nov 20, 2020 in CO and Architecture jothee 155 views
0 votes
4 answers
15
NIELIT 2016 MAR Scientist C - Section C: 19
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 389 views
0 votes
1 answer
16
NIELIT 2016 MAR Scientist C - Section C: 27
The process of entering data into a storage location causes variation in its address number adds to the contents of the location is called a readout operation is destructive of previous contents
The process of entering data into a storage location causes variation in its address number adds to the contents of the location is called a readout operation is destructive of previous contents
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 195 views
0 votes
1 answer
17
NIELIT 2016 MAR Scientist C - Section C: 28
Serial access memories are useful in applications where data consists of numbers short access time is required each stored word is processed differently data naturally needs to flow in and out in serial form
Serial access memories are useful in applications where data consists of numbers short access time is required each stored word is processed differently data naturally needs to flow in and out in serial form
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 137 views
0 votes
1 answer
18
NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 381 views
0 votes
2 answers
19
NIELIT 2016 MAR Scientist C - Section C: 46
Micro program is the name of source program in micro computers the set of instructions indicating the primitive operations in a system primitive form of macros used in assembly language programming program of very small size
Micro program is the name of source program in micro computers the set of instructions indicating the primitive operations in a system primitive form of macros used in assembly language programming program of very small size
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 204 views
0 votes
1 answer
20
NIELIT 2016 MAR Scientist C - Section C: 47
If a processor does not have any stack pointer register, then it cannot have subroutine call instruction it can have subroutine call instruction, but no nested subroutine calls nested subroutine calls are possible, but interrupts are not all sequences of subroutine calls and also interrupts are possible
If a processor does not have any stack pointer register, then it cannot have subroutine call instruction it can have subroutine call instruction, but no nested subroutine calls nested subroutine calls are possible, but interrupts are not all sequences of subroutine calls and also interrupts are possible
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 128 views
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