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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Recent questions in CO and Architecture

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1

coa question
Interpret the main memory addresses FF010,12364,andC7691 considering direct, associative and 2 way set associative mapping if the main memory size is 1MB,word size is 16 bytes, and cache size is 64KB.

1234hello asked in CO and Architecture Mar 11

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1 vote

1 answer

2

BARC 2015
Operand is fetched from memory During (A) fetch phase (B) execute phase (C) decode phase (D) read phase

dutta18 asked in CO and Architecture Mar 8

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3

self doubt
Can Interrupt-Driven I/O be memory mapped? Polling is memory mapped or IO mapped?

RutujaG asked in CO and Architecture Mar 7

61 views

1 vote

1 answer

4

pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)

Veeresh Badiger asked in CO and Architecture Mar 5

by Veeresh Badiger

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5

pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022) closed

Veeresh Badiger asked in CO and Architecture Mar 5

by Veeresh Badiger

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1 answer

6

With the help of the following information, determine the size of the sub-fields (in bits) in the address for direct mapping, associative mapping and set-associative mapping:  512 MB main memory and 2 MB cache memory  Address space of the processor is 256 MB  The block size is 256 bytes  There are 16 blocks in a cache set.

rookoodracula asked in CO and Architecture Mar 3

by rookoodracula

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1 answer

7

self doubt
true/ false cpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)

someshawasthi asked in CO and Architecture Feb 20

by someshawasthi

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2 votes

3 answers

8

GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third stages, respectively. Assume that there is no other ... instruction is fetched every cycle. The total execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$

admin asked in CO and Architecture Feb 15

by admin

1.1k views

2 votes

2 answers

9

GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check for a keystroke and consumes $100\; \mu \mathrm{s}$ (micro seconds) for ... interrupt and processing a keystroke. The ratio $\dfrac{T_{1}}{T_{2}}$ is _____________. (Rounded off to one decimal place)

admin asked in CO and Architecture Feb 15

by admin

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1 vote

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10

GATE CSE 2023 | Question: 31
Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. Which one of ... $(3,4,4, \text{L01)}$ $(8,1,1, \text{L02)}$ $(3,1,1, \text{L01)}$

admin asked in CO and Architecture Feb 15

by admin

1.1k views

1 vote

2 answers

11

GATE CSE 2023 | Question: 32
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip select $\text{(CS)}$ port of these memory blocks through a decoder as shown in the figure. The ... options is $\text{CORRECT}?$ $(0,1,2,3)$ $(0,1024,2048,3072)$ $(0,8,16,24)$ $(0,0,0,0)$

admin asked in CO and Architecture Feb 15

by admin

1.3k views

2 votes

1 answer

12

GATE CSE 2023 | Question: 35
Consider the $\textsf{IEEE-754}$ single precision floating point numbers $\text{P} = \textsf{0xC1800000}$ and $\text{Q} = \textsf{0x3F5C2EF4}.$ ... $\textsf{IEEE-754}$ single precision format? $\textsf{0x404C2EF4}$ $\textsf{0x405C2EF4}$ $\textsf{0xC15C2EF4}$ $\textsf{0xC14C2EF4}$

admin asked in CO and Architecture Feb 15

by admin

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1 vote

4 answers

13

GATE CSE 2023 | Question: 54
An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.

admin asked in CO and Architecture Feb 15

by admin

1.1k views

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0 answers

14

Relative Addressing Mode
Consider 3-word long jump instruction designed with PC-relative addressing mode, stored in the memory with a starting address of (2000)$_{10}$. Address field of an instruction contains (4000)$_{10}.$ Which of the following statements are true in the instruction ... where operand is stored, then how we can we assign it to PC? PC should be 2003 at the end of execution right?

Chaitanya Kale asked in CO and Architecture Feb 13

by Chaitanya Kale

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15

gate cs 2023
Do any one remember that COA question asked in gate cs 2023 where they have given some code and the options were like a) 3,1,1,L01 b)3,4,4,L01?

gaddalakonda_ganesh asked in CO and Architecture Feb 11

by gaddalakonda_ganesh

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1 answer

16

Unacademy Practice Question
Consider a 4 way set associative cache of size 16 KB organized into 4 words block. Cache memory is designed with the write back protocol having the miss ratio of read and write operations as 30% and 40% respectively. The tine taken by ... 50% read requests and 50% write requests. What is the average memory access time considering both read and write operations ?

Swarnava Bose asked in CO and Architecture Feb 1

by Swarnava Bose

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3 votes

0 answers

17

DMA stealing mode, where does extra 40ns come from?
Consider a disk with 4000 RPM rotational speed. The disk has 1K sectors on each track with 1k capacity of each sector. The disk is operating on the cycle stealing mode of DMA. It takes 50 nsec to transfer the 16 B data from disk to ... to DMA? This is the question here is the solution Can you tell where the 40ns which I have circled comes from??

h4kr asked in CO and Architecture Jan 31

by h4kr

106 views

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1 answer

18

Operand forwarding Made Easy Question
Consider 4-stage (IF, ID, EX, WB) pipeline used to execute the following code. All instructions are spending are spending one cycle on all the stages but ALU instructions are spending 3 cycles on 3rd stage. I1: LOAD R0, ... Number of cycles are saved using operand forwarding over without operand forwarding is? Can someone please explain by drawing the diagram?

Chaitanya Kale asked in CO and Architecture Jan 30

by Chaitanya Kale

195 views

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1 answer

19

Computer Organization and Architecture
Consider two cache organization which are byte addressable.In both cache organization cache size is 64 KB with 32-byte block.The first cache organization is direct mapped while the other is 4-way set associative.Physical address is of size ... latency of OR gate is 1 is.Find sum the latency of the direct mapped organization and set associative organization?

Sourin Kundu asked in CO and Architecture Jan 27

by Sourin Kundu

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20

COA
Which of the following is/are true for a CPU which does not have any stack pointer registers? A Interrupts are not possible. B All subroutine calls and interrupts are possible. C It cannot have nested subroutines call. D It cannot have subroutine call instruction.

Overflow04 asked in CO and Architecture Jan 25

120 views

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