Recent questions in CO & Architecture

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1

GATE 2019
The index node (inode) of a unix-like file system has 12 direct, one single-indirect and one double-indirect pointers. The disk block size is 4kB, and the disk block address is 32-bits long. The maximum possible file size is (rounded off to 1 decimal place) ___________ GB. [closed]

asked 2 days ago in CO & Architecture by Kuljeet Shan (309 points) | 58 views

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2

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

asked 5 days ago in CO & Architecture by DIYA BASU (241 points) | 16 views

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3

Self Doubt
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK

asked 5 days ago in CO & Architecture by DIYA BASU (241 points) | 16 views

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4

Self Doubt
Can someone provide me with the link of the answer key for Computer Organization(Zaky and Hamacher). Thanking you in advance:)

asked 6 days ago in CO & Architecture by DIYA BASU (241 points) | 23 views

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5

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache

asked Feb 17 in CO & Architecture by DIYA BASU (241 points) | 15 views

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6

Self-Doubt Priority interrupts
Under the SOFTWARE METHOD – POLLING heading. What is the meaning of this line? “In this method, all interrupts are serviced by branching to the same service program”. https://www.geeksforgeeks.org/priority-interrupts-sw-polling-daisy-chaining/

asked Feb 16 in CO & Architecture by amitqy Active (1.5k points) | 14 views

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1 answer

7

#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

asked Feb 14 in CO & Architecture by Reshu $ingh (345 points) | 44 views

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8

#MulticoreVSParallel
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?

asked Feb 13 in CO & Architecture by Reshu $ingh (345 points) | 34 views

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1 answer

9

#BookRecommendation
For Memory Addressing and Pipelining portion which standard book should I refer? Or any good resource to have crystal clear understanding,please suggest.

asked Feb 11 in CO & Architecture by Reshu $ingh (345 points) | 31 views

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1 answer

10

GATE-2000
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that (A) T1 <= T2 (B) T1 >= T2 (C) T1 < T2 (D) T1 is T2 plus the time taken for one ... instruction would take to execute in a non-pipelined system as it has only one unit.(I AM COMPARING ONLY THE TIME TAKEN BY A SINGLE INSTRUCTION).

asked Feb 10 in CO & Architecture by DIYA BASU (241 points) | 23 views

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1 answer

11

SELF DOUBT
In Single Precision floating point number when E=0 and M not equals to 0 it represents a fractional form..(BiAS=+127) when writing the decimal form why do we right (-1)^S * (1.M) * 2^(-126) instead of (-1)^S * (1.M) * 2^(-127)??

asked Feb 10 in CO & Architecture by DIYA BASU (241 points) | 24 views

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4 answers

12

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Feb 7 in CO & Architecture by Arjun Veteran (385k points) | 2.7k views

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2 answers

13

GATE2019-2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF

asked Feb 7 in CO & Architecture by Arjun Veteran (385k points) | 1.9k views

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4 answers

14

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

asked Feb 7 in CO & Architecture by Arjun Veteran (385k points) | 1.8k views

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1 answer

15

self doubt
How to do:(1000)base3 – (121)base3 without converting them to base 10 the final answer should be in base3

asked Feb 4 in CO & Architecture by DIYA BASU (241 points) | 52 views

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1 answer

16

gate 2019
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits

asked Feb 4 in CO & Architecture by sahil_malik (373 points) | 305 views

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17

SELF DOUBT
what is (120)base 10=( ? )base 64 ??

asked Feb 4 in CO & Architecture by DIYA BASU (241 points) | 82 views

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1 answer

18

Gate cse 2019
A certain processor deploy a single level-cache, the cache block size is 8 words, word size is 4 bytes, memory system uses 60mHz clock, to service a cache miss, the memory controller first takes 1 clock cycle to accept starting address of the block, ... bandwidth for the memory system when the program on the processor issues a series of read operation is _____________( yt s s )

asked Feb 4 in CO & Architecture by Mounikap (267 points) | 866 views

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19

COA booth algorithm self doubt
Why we do right shift in booth algorithm? I know the working of booths algorithm. Suppose we have multiplicand M = 01011 and multiplier Q = 01110 We can write Q as (2^4 - 2^1). So multiplication reduces to 2^4(M) + 2(-M) Now booths algorithm rules ... ^4(M) + 2(-M) we multiply by 16 and 2 which requires left shift. So how is booths algorithm working with right shift ?

asked Feb 4 in CO & Architecture by kd..... Junior (851 points) | 65 views

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2 answers

20

gate 2019

asked Feb 3 in CO & Architecture by pream sagar Active (1.7k points) | 376 views

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0 answers

21

self doubt
Main memory=512 words. block size=8 words. cache size =32 words There is an array A[100] and each element is 4 words then what is the hit ratio for the following loop. for(i=0;i<=9;i++) { for(j=0;j<=9;j=j+2) { A[i][j]=A[i][j]+20; } }

asked Feb 3 in CO & Architecture by DIYA BASU (241 points) | 84 views

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22

self doubt
Main memory=512 words. block size=8 words. cache size =32 words what is tag,line no.,block offset bits

asked Feb 3 in CO & Architecture by DIYA BASU (241 points) | 56 views

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23

self doubt
https://gateoverflow.in/2308/gate1993-11 This question can also be solved as a probability question where the random space contains (M1),(M1,M2),(M1,M2,M3) and let X be the random variable which gives the time for any of the three options selected from the ... space and correspondingly we give the PMF for each time selected and then we find the expectation?? Am I correct with my logic??

asked Feb 2 in CO & Architecture by DIYA BASU (241 points) | 28 views

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1 answer

24

SELF DOUBT
If main memory size=128KB. cache size 16KB . block size 256B. And memory is word addressable each word is 4B . Then is the address divided into : tag=3bits. line no=6 bits block offset=6 bits???(PLEASE VERIFY) We use DIRECT MAPPING.

asked Feb 2 in CO & Architecture by DIYA BASU (241 points) | 30 views

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25

Addresing modes
A computer has 64 bit instruction and 8 bit address.if there are 32 no of 3 address instruction and 248 no of 2 address instruction.how many 1 address instruction possible??

asked Feb 2 in CO & Architecture by Ssgmailcom (7 points) | 32 views

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26

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1 in CO & Architecture by newdreamz a1-z0 Active (1.6k points) | 47 views

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27

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1 in CO & Architecture by Aman Janko (47 points) | 21 views

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28

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1 in CO & Architecture by learner_geek Active (3.7k points) | 37 views

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29

made easy test series
please provide a detailed solution

asked Feb 1 in CO & Architecture by Vignaneswarkrishna (167 points) | 48 views

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30

Cache
Please tell what happens to hit rate, hit time, compulsory miss rate, conflict miss rate, capacity miss rate, miss time on : 1. Increasing Cache size 2. Increasing Block size 3. Increasing number of lines 4. Increasing Associativity

asked Jan 31 in CO & Architecture by Balaji Jegan Active (4.8k points) | 50 views

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