Recent questions in CO & Architecture

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1

Carl Hamacher Cache Memory
What should be correct answer to this question? In solution it's option A in Carl hamacher text book it's B ? I am confused please help

asked Jun 13 in CO & Architecture by vupadhayayx86 (47 points) | 64 views

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1 answer

2

about cache memory
For a system with two levels of cache, we define the following notation:  Tc1 = first-level cache access time  Tc2 = second-level cache access time  Tm = memory access time  H1 = first-level cache hit ratio  H2 = (first+second) level cache hit ratio. Provide an equation to calculate the average time of a read operation.

asked Jun 13 in CO & Architecture by komay (15 points) | 53 views

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1 answer

3

Branch Instruction
What is meaning of offset in Branch instruction? Is this offset same as conditional instruction offset? What is meaning of offset in virtual address? Where is actual difference between these two?

asked Jun 10 in CO & Architecture by srestha Veteran (86.8k points) | 30 views

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1 answer

4

Cache memory
Consider a scenario, where there is 2 level cache in a memory hierarchy. 1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instructions, then there will be 140 memory accesses. Here my question is how memory accesses can ... What miss rate is for L1,L2 and total in this memory hierarchy? Is it not number of misses in total number of instructions?

asked Jun 10 in CO & Architecture by srestha Veteran (86.8k points) | 39 views

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1 answer

5

practice
Q1 A RAM chip has a capacity of 1024 words of 8 bits each(1K x 8).The number of 2 x 4 decoders with enable line needed to construct a 16k x 16 RAM from 1K x 8 RAM is A 4 B. 5 C 6 D.7 Q2 The contents of flag register after execution of following pgm by 8085 microprocessor will be SUB A MVI B,(01)H DCR B HTL A (54)H B(00)H C (01)H D(45)H

asked Jun 9 in CO & Architecture by Prateek kumar Loyal (7.7k points) | 27 views

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1 answer

6

Computer Organization - Pipelining
What are stage delays in pipelining? Are they nothing but execution time required for each stage? and 'After pipelining we have to adjust the stage delays such that no stage will be waiting for another to ensure smooth pipelining (continuous flow) ' What does this statement means? Please give a brief explanation.

asked Jun 9 in CO & Architecture by Swapnil Naik (39 points) | 24 views

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7

Made Easy Test Series
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has ... 5+ (75+5-1)*3 Am i doing wrong? Solution with explanation of formulae being used will be welcomed.

asked Jun 9 in CO & Architecture by Subham Nagar Junior (539 points) | 40 views

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2 answers

8

pipelining
A CPU has five-stage pipeline where each stage takes 1ns, 2ns, 1.5ns, 3ns, 2.5ns. Instruction fetch happens in the first stage of the pipeline. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched ... one clock cycle. 30% of the instructions are conditional branches. Find the average execution time of the program for 1200 instructions is ________

asked Jun 7 in CO & Architecture by Amit puri Active (2.9k points) | 69 views

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1 answer

9

Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?

asked Jun 7 in CO & Architecture by srestha Veteran (86.8k points) | 43 views

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10

self doubt(carl hamacher,chapter1)
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of $500$ instruction including a $100$ instruction loop that is executed $25$ times.Determine the ratio of execution time without the cache to ... *24=7400$. my doubt is loop is occuring $25$ times so why there is multiplication of $24$ ??why not $25$??

asked Jun 4 in CO & Architecture by BASANT KUMAR (107 points) | 26 views

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11

Computer organization and architecture 10th edition #Problems 14.11

asked Jun 4 in CO & Architecture by Aaron (7 points) | 36 views

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0 answers

12

Vectored Interrupts
Are Vectored Interrupts possible in CPU having single Interrupt Request line? How/Why not?

asked Jun 2 in CO & Architecture by Harsh Kumar (189 points) | 21 views

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2 answers

13

Pipeline
Consider a 4 stage pipeline that consists of IF,ID,EX and WB stages.The time taken by these stages are 50ns,60ns,110ns and 80ns respectively.The pipeline registers are required after every pipeline stage and each of these pipeline registers consumes 10ns delay.What is the speedup of the pipeline under ideal conditions compare to the corresponding non-pipelined implementation?

asked May 31 in CO & Architecture by Sourav_35 (199 points) | 50 views

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14

WBUT 2012
A 30% enhancement in speedup for a component of the processor has been proposed for a new architecture.If the enhancement is usable only for 50% for the time,what is the fraction of the time must enhancement is used to achieve an overall speedup of 10?

asked May 31 in CO & Architecture by Sourav_35 (199 points) | 28 views

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1 answer

15

state exam
Program counter contains address of the Next programs to be fetched Previous programs to be fetched Previous information to be fetched Next information to be fetched

asked May 30 in CO & Architecture by VIDYADHAR SHELKE 1 (71 points) | 59 views

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2 answers

16

#CO and Architecture
There is a $5$ stage Instruction pipeline, which takes $1$ $ns$ to execute each cycle. There are $4000$ branch instructions with a delay of $2$ clock cycles and $6000$ normal instructions ( They get completed in $5$ stages). What will be the total execution ... time for execution will be $6004 + 4006 = 10010$ $ns$ Is this a correct answer and right way to solve such problem?

asked May 29 in CO & Architecture by Swapnil Naik (39 points) | 82 views

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1 answer

17

ComputerOrganizationCarlHamacherChap4ExcerciseQ10

asked May 27 in CO & Architecture by vupadhayayx86 (47 points) | 38 views

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1 answer

18

Addressing mode

asked May 27 in CO & Architecture by Prateek Raghuvanshi Active (3.9k points) | 47 views

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0 answers

19

Expand opcode technique
The format of a double operand instructions of a cpu consist of $4$ bit opcode and $4$ bit for source and destination.$12$ double operand instructions and $24$ single operand instructions must be implemented.Opcode field must identify the three groups ... operand instructions .what is the total no. of zero operand instructions that can be implemented? $512$ $516$ $521$ $523$

asked May 26 in CO & Architecture by Prateek Raghuvanshi Active (3.9k points) | 128 views

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1 answer

20

Self doubt regarding instruction format
As we know in register to register reference cpu ,for transfer operation we use $LOAD$ and $STORE$ instruction .Both are $2 -$address instruction ,instead of these two ,can we use $MOV$ instruction?? ,which is also $2-$address instruction used in transfer the data between memory and register.

asked May 25 in CO & Architecture by Prateek Raghuvanshi Active (3.9k points) | 39 views

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21

Avg. Access Time
When we calculate avg access time, If it is not given in question like it is Hierarchal or Simultaneous access then by default we have to take which access to calculate avg access time?

asked May 25 in CO & Architecture by jatinkumar (203 points) | 37 views

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1 answer

22

Computer organisation
If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.

asked May 24 in CO & Architecture by Shivani gaikawad (181 points) | 61 views

+1 vote

1 answer

23

ISI-MTECH-PCB 2018

asked May 19 in CO & Architecture by shefali1 Active (2k points) | 91 views

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1 answer

24

ace test series
Is Hardwire control system used for real time systems?

asked May 11 in CO & Architecture by Kartavya Kothari (81 points) | 44 views

+1 vote

2 answers

25

ace test series
A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting ‘40’ number of two address instructions, ‘400' number of one address instructions. The maximum number of zero address instructions that can be formulated is

asked May 11 in CO & Architecture by Kartavya Kothari (81 points) | 69 views

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1 answer

26

ACE TEST SERIES
Is the statement true or false; "RISC type processor is designed with minimum number of processing registers" ?

asked May 11 in CO & Architecture by Kartavya Kothari (81 points) | 55 views

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2 answers

27

addressing modes

asked May 10 in CO & Architecture by Sanjay Sharma Boss (48.2k points) | 53 views

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0 answers

28

ISI 2016 C2 B
The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For execution of the programs, the system utilizes ... in-status, check-status, branch and read/write in memory, each requiring one machine cycle. Please explain the solution with details.

asked May 10 in CO & Architecture by MiNiPanda Loyal (5.8k points) | 20 views

+1 vote

1 answer

29

Iitm ms/direct phd written test question

asked May 8 in CO & Architecture by Sambit Kumar Active (4k points) | 117 views

0 votes

1 answer

30

Calculate time taken for disk access time

asked May 8 in CO & Architecture by namastayinbed (7 points) | 61 views

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