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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Recent questions in CO and Architecture

1 vote
3 answers
1
NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 206 views
0 votes
2 answers
2
NIELIT 2016 DEC Scientist B (IT) - Section B: 37
How many address lines are needed to address each memory location in a $2048\times4$ memory chip? $10$ $11$ $8$ $12$
How many address lines are needed to address each memory location in a $2048\times4$ memory chip? $10$ $11$ $8$ $12$
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 137 views
1 vote
2 answers
3
NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 110 views
0 votes
1 answer
4
NIELIT 2016 DEC Scientist B (IT) - Section B: 55
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 92 views
1 vote
2 answers
5
NIELIT 2016 DEC Scientist B (CS) - Section B: 23
A nonpipelined system taken 50ns to process a task. the same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determinant the speedup ration of the pipeline for 100 tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$
A nonpipelined system taken 50ns to process a task. the same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determinant the speedup ration of the pipeline for 100 tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 109 views
0 votes
2 answers
6
NIELIT 2016 DEC Scientist B (CS) - Section B: 37
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
The principle of locality of reference justifies the use of Non reusable Cache memory Virtual memory None of the above
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 92 views
0 votes
1 answer
8
NIELIT 2016 DEC Scientist B (CS) - Section B: 53
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 72 views
0 votes
1 answer
9
NIELIT 2016 DEC Scientist B (CS) - Section B: 58
CPU consists of _______. ALU and Control Unit ALU, Control Unit and Monitor ALU, Control Unit and Hard disk ALU, Control Unit and Register
CPU consists of _______. ALU and Control Unit ALU, Control Unit and Monitor ALU, Control Unit and Hard disk ALU, Control Unit and Register
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 65 views
0 votes
1 answer
10
NIELIT 2017 July Scientist B (CS) - Section B: 22
What is the average Access Time for a drum rotating at $4000$ revolutions per minute? $2.5$ milliseconds $5.0$ milliseconds $7.5$ milliseconds $4.0$ milliseconds
What is the average Access Time for a drum rotating at $4000$ revolutions per minute? $2.5$ milliseconds $5.0$ milliseconds $7.5$ milliseconds $4.0$ milliseconds
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 67 views
0 votes
2 answers
11
NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle.
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle.
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 83 views
0 votes
2 answers
13
NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time is Same as the access time. Longer than the access time. Shorter than the access time. Multiple of the access time.
For a memory system, the cycle time is Same as the access time. Longer than the access time. Shorter than the access time. Multiple of the access time.
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 55 views
0 votes
1 answer
14
NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory has Lower bit density and higher power consumption Higher bit density and lower power consumption Lower bit density and lower power consumption None of the option
In comparison with static RAM memory, the dynamic RAM memory has Lower bit density and higher power consumption Higher bit density and lower power consumption Lower bit density and lower power consumption None of the option
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 54 views
0 votes
1 answer
15
NIELIT 2017 July Scientist B (CS) - Section B: 30
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\times 4$ bits? $13$ $14$ $16$ $17$
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\times 4$ bits? $13$ $14$ $16$ $17$
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 25 views
0 votes
3 answers
16
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 171 views
1 vote
4 answers
17
NIELIT 2017 DEC Scientist B - Section B: 6
A stack organized computer has which of the following instructions? zero-address one-address two-address three-address
A stack organized computer has which of the following instructions? zero-address one-address two-address three-address
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 201 views
0 votes
4 answers
18
NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage for clock skew and set up. What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 204 views
0 votes
2 answers
19
NIELIT 2017 DEC Scientist B - Section B: 14
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 108 views
0 votes
1 answer
20
NIELIT 2017 DEC Scientist B - Section B: 28
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________ $2^{12}$ $2^{10}$ $2^{19}$ $2^{13}$
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________ $2^{12}$ $2^{10}$ $2^{19}$ $2^{13}$
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 131 views
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