Recent questions in CO & Architecture

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1

gateforum_test_series
suppose that in a file organization record size(R)=150 bytes , block size (B)=512 bytes. there are totally 30000 records. the data field on which indexing is done is 9 bytes and block pointer size is 7 bytes how many block access will be needed to access a data item in case of single level primary indexing?

asked 1 hour ago in CO & Architecture by Shivam Kasat Junior (871 points) | 17 views

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2

co control word
Q:- micro programmed CU supports 400 control signals micro instruction is designed in such a way that 4 signals are active . What is the size of a control field in the instruction ?

asked 2 hours ago in CO & Architecture by hitendra singh Active (1.6k points) | 16 views

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3

Calculating average access time in multi level cache

asked 5 hours ago in CO & Architecture by Raj Singh 1 (23 points) | 6 views

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4

SELF DOUBT S
https://gateoverflow.in/1252/gate2007-54 IN THIS QUESTION ALLOPERANDS ARE IN MEMORY THEN SO WHY WE ARE ONLY MOVING a into REGISTER NOT MOVING b into register ?

asked 5 hours ago in CO & Architecture by eyeamgj Loyal (6.3k points) | 2 views

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5

Calculating cache penalty
For a system with two levels of cache, define $T_{c1}$ first-level cache access time; $T_{c2}$ second-level cache access time; $T_m$ memory access time; $H_1$ first-level cache hit ratio; $H_2$ combined first/second level cache hit ratio. Provide an equation for effective access time $T_a$ for a read operation.

asked 10 hours ago in CO & Architecture by Raj Singh 1 (23 points) | 8 views

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6

#pipeline
Consider execution of 100 instructions on a 5 stage pipeline. let P be the probability of an instruction being branch. The value of P such that speed up is atleast 4 is_____(assume each stage takes 1 cycle to perform its task and branch is predicted on forth stage of the pipeline)

asked 11 hours ago in CO & Architecture by Manan Shah (85 points) | 54 views

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7

gatebook test
Suppose the functions F and G can be computed in 8 and 3 nanoseconds by functional units UF and UG, respectively. Given three instances of UF and three instances of UG, it is required to implement the computation F(G(Xi)) for 1 ≤ i ≤ 13. A control Unit selects next task/s ... this computation is ( in nanoseconds): (A) 28 (B) 33 (C) 43 (D) 49 my answer is 43 but gatebook answer is 49.

asked 1 day ago in CO & Architecture by sushmita Boss (15.6k points) | 15 views

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8

gatebook COA test
Consider a program being run on a processor. A modification in processor design caused 30% of the program to speed up by ten times while three fourth of the remaining program has a speed up of 80 and 40% of the remaining part of the program performs poorer ... by 50%. The remaining program has a speedup of 1. The overall speedup of the program exact to two decimal places is:-

asked 1 day ago in CO & Architecture by sushmita Boss (15.6k points) | 20 views

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1 answer

9

Pipeline
A pipelined Processor contains 5 instructions stages of execution times 120ns, 160ns, 105 ns, 135ns and 155ns with a register delay 10ns on each stage. What is the percentage of performance increased with 1000 instructions instead of 10 instructions

asked 1 day ago in CO & Architecture by aditi19 Active (2.2k points) | 46 views

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10

Direct Mapping and set associative Mapping

asked 1 day ago in CO & Architecture by Shaik Masthan Boss (43.3k points) | 116 views

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11

Self Doubt
Conflict misses and inference misses reduces can be reduced by doubling the associativity of cache design? True or False with some explanation

asked 1 day ago in CO & Architecture by Shadan Karim (381 points) | 10 views

+1 vote

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12

https://gateoverflow.in/753/gate2001-12?show=279851#c279851

asked 1 day ago in CO & Architecture by sushmita Boss (15.6k points) | 24 views

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13

Set associative cache implementation
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Show how cache interprets the processor’s addresses.

asked 1 day ago in CO & Architecture by Raj Singh 1 (23 points) | 21 views

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14

#CO #2-Level Memory Hierarchy
What should be the answer and explanation for this question? https://gateoverflow.in/?qa=blob&qa_blobid=12048400696649494741

asked 1 day ago in CO & Architecture by `JEET Active (2.3k points) | 10 views

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15

general doubt on pipelining
we do forwarding from WB stage to EX or from WB to MEM stage??

asked 1 day ago in CO & Architecture by sushmita Boss (15.6k points) | 25 views

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16

confusion
What is the difference between ‘performance gain’ and ‘speed up’?

asked 2 days ago in CO & Architecture by mks_cse (137 points) | 7 views

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1 answer

17

Self doubt
A micro programmed control unit uses one address instruction for control word sequencing. Based on the behaviour of control signals,the control signal field is divided into 6 groups. Each group contains mutually exclusive control signals. The following table ... 16 How many bits are saved in control field with respect to horizontal micro programming What is max degree of parallelism

asked 2 days ago in CO & Architecture by Vipin Rai (391 points) | 15 views

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1 answer

18

COA-1 ME Test Series
A system employs $10$ stage instruction pipeline in which $5$% instruction results in data dependency, $10$% instruction results in control dependency, $2$% instructions results in structural dependency. $10$% instructions are exposed to data and control ... and data dependency are $3$ clocks and $2$ clocks respectively. The average instruction time is _______ [in cycles]

asked 2 days ago in CO & Architecture by zeeshanmohnavi (137 points) | 184 views

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19

ME TEST SERIES
Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents number of compulsory ... = 2 and conflict = 18 Compulsory = 3 and conflict = 18 Compulsory = 3 and conflict = 16 .None of these [closed]

asked 3 days ago in CO & Architecture by Vivekk (403 points) | 16 views

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20

Refresh overhead
Explain the refresh overhead in dram?

asked 3 days ago in CO & Architecture by Mayank Gupta 3 Junior (505 points) | 7 views

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21

Register renamimg
Give an example where register renamimg helps in eliminating the hazards

asked 4 days ago in CO & Architecture by Mayank Gupta 3 Junior (505 points) | 10 views

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22

SELF DOUBT
https://gateoverflow.in/61144/ugcnet-june2015-iii-5 NOT GETTING AT LAST …….

asked 4 days ago in CO & Architecture by eyeamgj Loyal (6.3k points) | 10 views

+1 vote

0 answers

23

DMA and Interrupt mechanism
DMA does issue an interrupt for bus request after the transfer is complete from I/O device to disk(i.e. after the preparation time) right ?

asked 4 days ago in CO & Architecture by Ashwani Yadav (423 points) | 63 views

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24

Testbook subject test
what is the meaning of assertion.I know PC requires 1 memory access but they said 2.

asked 4 days ago in CO & Architecture by Mayank Gupta 3 Junior (505 points) | 9 views

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25

TESTBOOK COA

asked 4 days ago in CO & Architecture by Mayank Gupta 3 Junior (505 points) | 40 views

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26

Self Doubt
How to find the number of mux required in a k-way set associative cache? Please give the implementation of the same.

asked 4 days ago in CO & Architecture by Vipin Rai (391 points) | 13 views

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1 answer

27

made easy test series
consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and there are 1.8 memory references per instruction, then average stall per instruction is 6.36 7.92 9.62 9.35

asked 4 days ago in CO & Architecture by scarz (51 points) | 38 views

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28

Hard disk data transfer rate , data rate

asked 5 days ago in CO & Architecture by Mayank Gupta 3 Junior (505 points) | 14 views

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29

Cache organisation
Do we use multiplexer in direct mapped cache ?

asked 5 days ago in CO & Architecture by Mayank Gupta 3 Junior (505 points) | 13 views

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30

ace Q

asked 5 days ago in CO & Architecture by kallu singh Junior (937 points) | 19 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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