Recent questions in CO & Architecture

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1

Subroutine for adding array
Subroutine for adding column x to column y element by element , leaving the sum element in column y

asked 3 hours ago in CO & Architecture by prajabobde (9 points) | 4 views

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2

Control sequence to add the contents of memory location whose address is at memory location num to register r1

asked 13 hours ago in CO & Architecture by prajabobde (9 points) | 9 views

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3

addressing modes in coa.
A computer supports one address and two address instructions. All the Addresses are the memory addresses. Memory size is 1Mbyte. How many one address instructions are possible if it has 240 two addresses instructions? (Assume binary instructions code has 48 bits)

asked 1 day ago in CO & Architecture by ritus (27 points) | 15 views

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4

Memory Hierarchy
if simply the access time of level-1 meomry and level-2 memory is given and hit ratio is given then for average time access what should be the approach? should i go for hierarchical or simultaneous access?

asked 1 day ago in CO & Architecture by Nihar Ranjan Panda (33 points) | 20 views

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5

Patterson-Henessey, Pipelining
Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been written into the register file and so, there should be three stalls? From what I could understand in this question, the value of the registers is available after the M stage, before it is written.

asked 2 days ago in CO & Architecture by goxul Active (1.1k points) | 8 views

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6

Self doubt
In case of CISC, why more number of addressing modes helps in faster exectuion of program?

asked 3 days ago in CO & Architecture by Anuranjan Chauhan (277 points) | 17 views

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7

self doubt(NPTEL assignment)
Encode the instruction sub r1, r2, 3 (a) 00001 0 0001 0010 00 0000 0000 0000 0011 (b)00001 1 0001 0010 00 0000 0000 0000 0011 (c) 00011 1 0001 0010 00 0000 0000 0000 0111 (d)None of the above

asked 3 days ago in CO & Architecture by BASANT KUMAR Junior (919 points) | 18 views

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8

computer organization and architecture
what is meaning of vectored interrupt... in vectored interrupt all device have separate interrupt request line or one single interrupt request line common for all io devices ? and what is the purpose of INTA signal?

asked 3 days ago in CO & Architecture by Rahul_Rathod_ (363 points) | 15 views

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9

Two level of cache
Consider a two level cache system. For 100 memory references 20 misses in 1st level cache,10 misses in second level cache. Miss penalty from second level to memory is 40 cycles. if Total average = 7.6 cycles, then hit time of second level cache ? Assume hit time of second level cache is two times the first level cache? Ans. 4

asked 4 days ago in CO & Architecture by Na462 Active (4.6k points) | 65 views

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10

Explain this. And explain mapping. Just confuse between words per block. Per word n etc

asked 4 days ago in CO & Architecture by Aman mourya (15 points) | 20 views

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11

Computer organization

asked 4 days ago in CO & Architecture by BHASHKAR (11 points) | 42 views

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12

Addressing modes
Instructions are stored in memory. When they are to be executed they are brought into instruction register. Now it is divided as Mode, opcode, operand (log (memory size) is divided in three parts) . In direct addressing, operand represent the effective ... required to address a memory then how such a big instruction is stored in memory whose operand itself has those many bits?

asked 5 days ago in CO & Architecture by tusharp Junior (805 points) | 26 views

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13

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked 6 days ago in CO & Architecture by Na462 Active (4.6k points) | 11 views

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14

Control Memory

asked 6 days ago in CO & Architecture by Na462 Active (4.6k points) | 10 views

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15

Test Series
Consider a processor uses 2 byte instruction format. Processor has 32 Registers and supports upto 2-Address instructions. If processor supports 128 1 Address instructions then number of 2-Address Instructions are? [closed]

asked Aug 12 in CO & Architecture by Manish Chetwani (291 points) | 22 views

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16

carl hamacher(chapter 2 )
in the underline statement it is given that higher performance can be achieved if each instruction occupy one word???how it is true??what happen when two instruction occupy in single word???

asked Aug 11 in CO & Architecture by BASANT KUMAR Junior (919 points) | 15 views

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17

harddisk
Consider magnetic disk with the following parameters: Average seek time = 12 ms Rotation rate = 3600 RPM Transfer rate = 3.5 MB/second # of Sectors per track = 64 Sector size =512 bytes Controller overhead =5.5 ms What is the average time to read 8 KB in ... only 8KB? Is it like same cylinder means no need to multiply by 16 and if given different cylinder then we need to consider 8kB*16?

asked Aug 11 in CO & Architecture by Amit puri Active (3k points) | 11 views

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18

cache memory
Consider a cache of size 64 bytes, with block size 16 bytes and main memory is divided into blocks of 16 bytes each i.e. block 0 has address 0 to 15 so on. Consider the following program that access memory in given sequence: 1.Access address 63 through 70 2.Loop i) 15 ... line 0 contain address 0, 4, 8 etc. and line 1 contain address 1, 5, 7 etc. and so on.) [Upto 2 decimal places]

asked Aug 10 in CO & Architecture by Deepalitrapti (217 points) | 10 views

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19

DMA Device
Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cycle take 2 μsec. What is the data transfer rate of DMA?

asked Aug 10 in CO & Architecture by Deepalitrapti (217 points) | 7 views

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1 answer

20

misses and hit
Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents number of compulsory and conflict misses?

asked Aug 10 in CO & Architecture by Deepalitrapti (217 points) | 18 views

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21

Cache Mapping
Consider a 16-way set associative cache which holds 64 KB of data. The size of physical address is of 40 bits. A cache block consist of 4 words. Every data word is of 32 bits. Assuming that all cache entries are initially empty and data words are word-addressable. Find the size of Tag , Set and Offset field in bits?

asked Aug 8 in CO & Architecture by ben10 (149 points) | 6 views

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22

test series
A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 106 instructions per second. An average instruction requires six processor cycles, three ... instruction per sec how? my assumption is in 1 sec both 95% and 5% of instruction should be executed .may i right or wrong ?

asked Aug 8 in CO & Architecture by Anshu Singh Suryavan (73 points) | 7 views

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23

Addressing Mode
Consider the following expression used to execute on a stack CPU X = (A × B)+C, where all the variables are in the memory. What is the number of zero and one address instructions are required respectively to evaluate the expression?

asked Aug 7 in CO & Architecture by ben10 (149 points) | 10 views

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24

Cache Capacity
if in a question it ask for cache capacity the is it calculated by follwing... cache capacity=cache size+ tag memory size+dirty bit cache capacity=tag bits * no. of cache lines which one is correct?

asked Aug 6 in CO & Architecture by Nihar Ranjan Panda (33 points) | 21 views

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25

test series
Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of the total instructions. If the miss penalty is 30 clock cycles and the miss rate is 4%, how much faster would the computer be if all instructions were cache hits?

asked Aug 6 in CO & Architecture by Anshu Singh Suryavan (73 points) | 3 views

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26

Chip Select
Ans. C

asked Aug 6 in CO & Architecture by Na462 Active (4.6k points) | 8 views

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1 answer

27

Multilevel Cache Access time
Ans. A

asked Aug 6 in CO & Architecture by Na462 Active (4.6k points) | 46 views

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28

Signed 2's complement Exponent

asked Aug 6 in CO & Architecture by Na462 Active (4.6k points) | 18 views

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29

IEEE Double Precision
Ans. D

asked Aug 6 in CO & Architecture by Na462 Active (4.6k points) | 16 views

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30

performance of cache memory
in cache performace i have confusion about where to use which formula like for write through whether use H (tc) + (1-H) (tc+m) or H (tc) + (1-H) (m) and how to identify whether cache memory is hierarchical or not from question can anyone give me all formula related to cache performance with explanation

asked Aug 6 in CO & Architecture by Rahul_Rathod_ (363 points) | 15 views

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