Recent questions in CO & Architecture

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1

Self Doubt-Little/big endian-GeeksforGeeks
#include <stdio.h> int main() { unsigned char arr[2] = {0x01, 0x00}; unsigned short int x = *(unsigned short int *) arr; printf("%d", x); getchar(); return 0; } Output in little endian and big endian ? Please someone provide a detailed explanation if possible with diagram.

asked Jun 9 in CO & Architecture by Masterk (99 points) | 33 views

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1 answer

2

No of bits required to encode instructions
A computer has the following ISA and description - LOAD and STORE instructions capable of storing data from the accumulator to memory locations with indirect mode taking the argument as a register MOV capable of copying data from one register to another ADD ... 5 bit offset Min no of bits required to encode all the instructions above ?? Is it 4 bits ??

asked Jun 4 in CO & Architecture by s_dr_13 (119 points) | 25 views

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3

Indirect Addressing Mode
Consider an instruction of indirect addressing mode. What are the number of memory references by the processor when instruction is a computation that requires a single operand and when it is an unconditional branch instruction respectively ?? 3,3 3,2 2,2 4,3 I believe the answer is B Correct me

asked Jun 4 in CO & Architecture by s_dr_13 (119 points) | 19 views

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1 answer

4

IEEE 754 Standard
In IEEE 754 single floating point format, how many numbers can be represented in the interval [10, 16)? A. B. 3 x 2^21 C. 5 X 2^21 D. 2^22

asked Jun 3 in CO & Architecture by s_dr_13 (119 points) | 37 views

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5

Bits HD 2019
In a microprocessor, size of register is generally: Lesser than the size of the data it operates on Greater than the size of the data it operates on Equal to the size of the data it operates on

asked May 29 in CO & Architecture by manikgupta123 (75 points) | 39 views

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1 answer

6

RISC JUMP INSTRUCTION SELF DOUBT
Why can’t we keep target32 address in the 32 bit registers of the RISC instruction? Why is it have to be t J target26 instead of J target32 ?

asked May 26 in CO & Architecture by Gitika Babbar (119 points) | 25 views

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2 answers

7

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

asked May 24 in CO & Architecture by Gitika Babbar (119 points) | 49 views

+1 vote

1 answer

8

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

asked May 23 in CO & Architecture by Hirak Active (3k points) | 42 views

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9

Number System (self doubts)
mam how convert into hexadecimal

asked May 22 in CO & Architecture by altamash (389 points) | 19 views

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10

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

asked May 21 in CO & Architecture by Ritabrata Dey (29 points) | 21 views

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1 answer

11

Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(

asked May 20 in CO & Architecture by srestha Veteran (111k points) | 38 views

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12

ROM(self doubts)
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits)

asked May 19 in CO & Architecture by altamash (389 points) | 14 views

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2 answers

13

Direct Mapped Cache Multiplexer
Is there any multiplexer(s) present in the implementation of Direct Mapped Cache? If yes, then the Hit latency would be Multiplexer latency + Comparator Latency?

asked May 16 in CO & Architecture by Sumiran Agrawal (91 points) | 75 views

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14

set associative (carl hamacher)
Block set associative cache consists of a total of 64blocks divided into 4blocks sets .The main memory contains 4096blocks ,each consisting of 128 words. how many bits for Main memory how many bits for TAG,SET,WORD . solution: MM=block size*words 2^12 * 2^7=19 bits TAG=9 SET=4 WORD=6 is this correct method or not please correct me

asked May 13 in CO & Architecture by altamash (389 points) | 18 views

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15

No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.

asked May 7 in CO & Architecture by Tuhin Dutta Loyal (9k points) | 46 views

0 votes

1 answer

16

NTA NET DEC 2018-53
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is- 0xC2006000 0xC2006666 0xC2206000 0xC2206666

asked May 7 in CO & Architecture by Kuljeet Shan Active (1.5k points) | 88 views

0 votes

1 answer

17

IIIT PGEE 2019
Which part in 8086 microprocessor is responsible for fetching instructions into the queue? BIU EU Stack Registers

asked Apr 29 in CO & Architecture by manikgupta123 (75 points) | 63 views

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18

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked Apr 17 in CO & Architecture by srestha Veteran (111k points) | 48 views

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19

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked Apr 16 in CO & Architecture by Ritabrata Dey (29 points) | 22 views

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20

Goldman Sachs Screening Test
In Matrix Multiplication Operation Code uses Temporal Locality and Data uses Spatial Locality Data uses Temporal Locality and Code uses Spatial Locality Both data and code uses Spatial Locality Both data and code uses Temporal Locality

asked Apr 14 in CO & Architecture by ved (5 points) | 14 views

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21

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12 in CO & Architecture by Miny (139 points) | 6 views

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22

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2 in CO & Architecture by srestha Veteran (111k points) | 45 views

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1 answer

23

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

asked Apr 1 in CO & Architecture by aditi19 Active (3.7k points) | 66 views

+1 vote

1 answer

24

Allen Career Institute:Computer Organization -Memory
The size of instruction in a single accumulator CPU organization is $16$ bits. In order to evaluate the expressions given below. How much memory space (bytes) is required for storing the program? evaluate the expression from left to right). Expression : $y=\frac{A-B+C}{E+F}$

asked Mar 22 in CO & Architecture by srestha Veteran (111k points) | 48 views

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25

self-doubt
How do we perform 0 – 1 in 2’s complement subtraction using 1-bit register??

asked Mar 21 in CO & Architecture by Doraemon (179 points) | 21 views

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26

CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20 in CO & Architecture by Devshree Dubey Boss (13.6k points) | 23 views

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27

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18 in CO & Architecture by Doraemon (179 points) | 32 views

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28

Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)

asked Mar 17 in CO & Architecture by Anuranjan (43 points) | 14 views

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29

Cache Memory and Arrays
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.

asked Mar 16 in CO & Architecture by amitqy Active (1.8k points) | 14 views

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30

Self-doubt
What is actually meant by average access time experienced by processor?

asked Mar 14 in CO & Architecture by Anuranjan (43 points) | 15 views

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