Recent questions in CO & Architecture

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1

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked 5 days ago in CO & Architecture by srestha Veteran (111k points) | 17 views

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2

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked Apr 16 in CO & Architecture by Ritabrata Dey (37 points) | 18 views

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3

Goldman Sachs Screening Test
In Matrix Multiplication Operation Code uses Temporal Locality and Data uses Spatial Locality Data uses Temporal Locality and Code uses Spatial Locality Both data and code uses Spatial Locality Both data and code uses Temporal Locality

asked Apr 14 in CO & Architecture by ved (9 points) | 11 views

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4

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12 in CO & Architecture by Miny (149 points) | 5 views

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5

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2 in CO & Architecture by srestha Veteran (111k points) | 36 views

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1 answer

6

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

asked Apr 1 in CO & Architecture by aditi19 Active (2.9k points) | 58 views

+1 vote

1 answer

7

Allen Career Institute:Computer Organization -Memory
The size of instruction in a single accumulator CPU organization is $16$ bits. In order to evaluate the expressions given below. How much memory space (bytes) is required for storing the program? evaluate the expression from left to right). Expression : $y=\frac{A-B+C}{E+F}$

asked Mar 22 in CO & Architecture by srestha Veteran (111k points) | 37 views

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8

self-doubt
How do we perform 0 – 1 in 2’s complement subtraction using 1-bit register??

asked Mar 21 in CO & Architecture by Doraemon (195 points) | 18 views

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9

CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20 in CO & Architecture by Devshree Dubey Boss (14k points) | 16 views

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10

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18 in CO & Architecture by Doraemon (195 points) | 24 views

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11

Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)

asked Mar 17 in CO & Architecture by Anuranjan (61 points) | 13 views

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12

Cache Memory and Arrays
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.

asked Mar 16 in CO & Architecture by amitqy Active (1.9k points) | 13 views

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13

Self-doubt
What is actually meant by average access time experienced by processor?

asked Mar 14 in CO & Architecture by Anuranjan (61 points) | 14 views

+1 vote

1 answer

14

Self-doubt
What is meant by cache index? Please state by example.

asked Mar 13 in CO & Architecture by Anuranjan (61 points) | 42 views

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15

selfdoubt
Show how to do the following statement c = a[2] + b[0] a) using register direct, imm, register indirect b) using register direct, imm, absolute addressing c) using register direct, imm, register indirect with displacement

asked Mar 13 in CO & Architecture by manisha11 Active (2k points) | 41 views

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1 answer

16

NTA NET DEC 2018

asked Mar 12 in CO & Architecture by Kuljeet Shan Active (1.1k points) | 38 views

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17

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles). [closed]

asked Mar 10 in CO & Architecture by s_dr_13 (133 points) | 42 views

+1 vote

1 answer

18

Self-doubt
What does tag number signifies in line in cache?

asked Mar 10 in CO & Architecture by Anuranjan (61 points) | 26 views

+1 vote

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19

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

asked Mar 8 in CO & Architecture by s_dr_13 (133 points) | 39 views

–1 vote

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20

GradeUp COA
If a processor has 64 address lines and 8 data lines. Then find maximum number of opcodes generated by processor. a)6 b)9 c)3 d)8 [closed]

asked Feb 24 in CO & Architecture by Abhisek Tiwari 4 Active (4.4k points) | 126 views

+1 vote

1 answer

21

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

asked Feb 18 in CO & Architecture by DIYA BASU (289 points) | 44 views

+1 vote

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22

Self Doubt
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK

asked Feb 18 in CO & Architecture by DIYA BASU (289 points) | 29 views

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1 answer

23

Self Doubt
Can someone provide me with the link of the answer key for Computer Organization(Zaky and Hamacher). Thanking you in advance:)

asked Feb 17 in CO & Architecture by DIYA BASU (289 points) | 41 views

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1 answer

24

Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>set associative cache

asked Feb 17 in CO & Architecture by DIYA BASU (289 points) | 33 views

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1 answer

25

Self-Doubt Priority interrupts
Under the SOFTWARE METHOD – POLLING heading. What is the meaning of this line? “In this method, all interrupts are serviced by branching to the same service program”. https://www.geeksforgeeks.org/priority-interrupts-sw-polling-daisy-chaining/

asked Feb 16 in CO & Architecture by amitqy Active (1.9k points) | 24 views

+1 vote

1 answer

26

#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

asked Feb 14 in CO & Architecture by Reshu $ingh (369 points) | 52 views

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27

#MulticoreVSParallel
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?

asked Feb 13 in CO & Architecture by Reshu $ingh (369 points) | 55 views

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1 answer

28

#BookRecommendation
For Memory Addressing and Pipelining portion which standard book should I refer? Or any good resource to have crystal clear understanding,please suggest.

asked Feb 11 in CO & Architecture by Reshu $ingh (369 points) | 40 views

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1 answer

29

GATE-2000
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that (A) T1 <= T2 (B) T1 >= T2 (C) T1 < T2 (D) T1 is T2 plus the time taken for one ... instruction would take to execute in a non-pipelined system as it has only one unit.(I AM COMPARING ONLY THE TIME TAKEN BY A SINGLE INSTRUCTION).

asked Feb 10 in CO & Architecture by DIYA BASU (289 points) | 29 views

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1 answer

30

SELF DOUBT
In Single Precision floating point number when E=0 and M not equals to 0 it represents a fractional form..(BiAS=+127) when writing the decimal form why do we right (-1)^S * (1.M) * 2^(-126) instead of (-1)^S * (1.M) * 2^(-127)??

asked Feb 10 in CO & Architecture by DIYA BASU (289 points) | 35 views

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