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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

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\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

+2 votes

2 answers

ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $ADD, SUB$ and $MOV$. Consider $2$ ... is better in terms of memory accesses and by how many $MOV$ instructions ? Case $2,2$ Case $2,3$ Case $1,2$ Case $1,3$

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 302 views

+1 vote

1 answer

ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 230 views

+1 vote

1 answer

ISRO2020-6
A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2 ..,R12)$. Following operations are supported $ADD\ Ra,\ Rb,\ Rr$ Add $Ra$ to $Rb$ and store the result in $Rr$ $MUL\ Ra,\ Rb,\ Rr$ Multiply $Ra$ to $Rb$ and store the result in $Rr$ $MUL$ ... $X,Y,Z$ are initially available in registers $R0,R1$ and $R2$ and contents of these registers must not be modified. $5$ $6$ $7$ $8$

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 232 views

+2 votes

1 answer

ISRO2020-5
An array of $2$ ...

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 217 views

+3 votes

2 answers

ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 297 views

+1 vote

2 answers

ISRO2020-46
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes? $1,280,000$ $1280$ $1250$ $128,000$

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 268 views

+1 vote

2 answers

ISRO2020-43
Which of the following is an efficient method of cache updating ? Snoopy writes Write through Write within Buffered write

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 209 views

+2 votes

1 answer

ISRO2020-49
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called True dependency Anti-dependency Output dependency Control Hazard

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 125 views

+1 vote

1 answer

ISRO2020-3
Which of the following affects the processing power assuming they do not influence each other Data bus capability Address scheme Clock speed $3$ only $1$ and $3$ only $2$ and $3$ only $1,2$ and $3$

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 135 views

+1 vote

3 answers

ISRO2020-2
Statements associated with registers of a CPU are given. Identify the false statement. The program counter holds the memory address of the instruction in execution Only opcode is transferred to the control unit An instruction in the instruction register consists of the ... The value of the program counter is incremented by $1$ once its value has been read to the memory address register

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 180 views

+1 vote

1 answer

ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 113 views

+2 votes

2 answers

ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 159 views

+2 votes

2 answers

ISRO2020-7
Consider a $5$- segment pipeline with a clock cycle time $20$ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$

asked Jan 13 in CO and Architecture by Satbir Boss (25.1k points) | 286 views

0 votes

0 answers

NTA NET DEC 2019 (microprocessor)

asked Dec 30, 2019 in CO and Architecture by Sanjay Sharma Boss (49.4k points) | 92 views

+3 votes

1 answer

NTA NET DEC 2019 (micro operation)
Match List I List II a) Micro operation (i) Specify micro operation b) Microprogrammed control unit (ii) Improve CPU utilization c) Interrupts (iii) Control Memory d) Micro instruction (Iv) Elementary operation performed on data stored in registers Choose the correct option from these given below 1) ... ii 3) a-iii , b-iv , c- i , d-ii 4) a-iii , b-iv , c-ii , d-i

asked Dec 27, 2019 in CO and Architecture by Sanjay Sharma Boss (49.4k points) | 67 views

+1 vote

1 answer

WEST BENGAL SET COMPUTER SCIENCE

asked Sep 22, 2019 in CO and Architecture by Jit Saha 1 (27 points) | 94 views

+2 votes

1 answer

WEST BENGAL SET COMPUTER SCIENCE

asked Sep 22, 2019 in CO and Architecture by Jit Saha 1 (27 points) | 64 views

+4 votes

3 answers

UGCNET-June-2019-II-11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed

asked Jul 2, 2019 in CO and Architecture by Arjun Veteran (434k points) | 525 views

+2 votes

2 answers

UGCNET-June-2019-II-12
Suppose that the register $A$ and the register $K$ have the bit configuration. Only the three leftmost bits of $A$ are compared with memory words because $K$ has $1$'s in these positions. Because of its organization, this type of ... is uniquely suited to parallel searches by data association. This type of memory is known as RAM ROM content addressable memory secondary memory

asked Jul 2, 2019 in CO and Architecture by Arjun Veteran (434k points) | 271 views

+1 vote

1 answer

UGCNET-June-2019-II-14
The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents of flags and counters registers and counters flags and registers flags, registers and counters

asked Jul 2, 2019 in CO and Architecture by Arjun Veteran (434k points) | 258 views

+1 vote

4 answers

UGCNET-June-2019-II-19
How many address lines and data lines are required to provide a memory capacity of $16 K \times 16$? $10, \:4$ $16, \: 16$ $14, \:16$ $4, \:16$

asked Jul 2, 2019 in CO and Architecture by Arjun Veteran (434k points) | 311 views

+1 vote

2 answers

UGCNET-June-2019-II-20
Suppose that a computer program takes $100$ seconds of execution time on a computer with multiplication operation responsible for $80$ seconds of this time. How much do you have to improve the speed of the multiplication operation if you are asked to execute this program four times faster? $14$ times faster $15$ times faster $16$ times faster $17$ times faster

asked Jul 2, 2019 in CO and Architecture by Arjun Veteran (434k points) | 275 views

+1 vote

2 answers

UGCNET-June-2019-II-49
A processor can support a maximum memory of $4$ GB where memory is word addressable and a word is $2$ bytes. What will be the size of the address bus of the processor? At least $28$ bits At least $2$ bytes At least $31$ bits Minimum $4$ bytes

asked Jul 2, 2019 in CO and Architecture by Arjun Veteran (434k points) | 153 views

–1 vote

0 answers

Self Doubt-Little/big endian-GeeksforGeeks
#include <stdio.h> int main() { unsigned char arr[2] = {0x01, 0x00}; unsigned short int x = *(unsigned short int *) arr; printf("%d", x); getchar(); return 0; } Output in little endian and big endian ? Please someone provide a detailed explanation if possible with diagram.

asked Jun 9, 2019 in CO and Architecture by Kushagra गुप्ता Loyal (5.6k points) | 93 views

0 votes

1 answer

No of bits required to encode instructions
A computer has the following ISA and description - LOAD and STORE instructions capable of storing data from the accumulator to memory locations with indirect mode taking the argument as a register MOV capable of copying data from one register to another ADD ... 5 bit offset Min no of bits required to encode all the instructions above ?? Is it 4 bits ??

asked Jun 4, 2019 in CO and Architecture by s_dr_13 (417 points) | 95 views

0 votes

1 answer

Indirect Addressing Mode
Consider an instruction of indirect addressing mode. What are the number of memory references by the processor when instruction is a computation that requires a single operand and when it is an unconditional branch instruction respectively ?? 3,3 3,2 2,2 4,3 I believe the answer is B Correct me

asked Jun 4, 2019 in CO and Architecture by s_dr_13 (417 points) | 71 views

+2 votes

1 answer

IEEE 754 Standard
In IEEE 754 single floating point format, how many numbers can be represented in the interval [10, 16)? A. B. 3 x 2^21 C. 5 X 2^21 D. 2^22

asked Jun 3, 2019 in CO and Architecture by s_dr_13 (417 points) | 163 views

0 votes

0 answers

Bits HD 2019
In a microprocessor, size of register is generally: Lesser than the size of the data it operates on Greater than the size of the data it operates on Equal to the size of the data it operates on

asked May 29, 2019 in CO and Architecture by manikgupta123 (81 points) | 108 views

0 votes

1 answer

RISC JUMP INSTRUCTION SELF DOUBT
Why can’t we keep target32 address in the 32 bit registers of the RISC instruction? Why is it have to be t J target26 instead of J target32 ?

asked May 26, 2019 in CO and Architecture by Gitika Babbar (157 points) | 49 views

0 votes

2 answers

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

asked May 24, 2019 in CO and Architecture by Gitika Babbar (157 points) | 220 views

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