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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Most answered questions in CO and Architecture

0 votes
4 answers
122
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on theStack pointerAccumulatorProgram counterStack
1 votes
4 answers
124
0 votes
4 answers
125
2 votes
4 answers
127
INCA(Increase register A by $1$) is an example of which of the following addressing mode?Immediate addressingIndirect addressingImplied addressingRelative addressing
8 votes
4 answers
130
An array of $2$ two byte integers is stored in big endian machine in byte addresses as shown below. What will be its storage pattern in little endian machine ?$$\begin{ar...
1 votes
4 answers
133
1 votes
4 answers
134
How many address lines and data lines are required to provide a memory capacity of $16 K \times 16$?$10, \:4$$16, \: 16$$14, \:16$$4, \:16$
0 votes
4 answers
138
Match the items in $\textbf{List-I}$ and $\textbf{List-II}$ :$\begin{array}{clcl} {} & {\textbf{List-I}} & {} & {\textbf{List-II}} \\ \text{(a)} & \text{interrupts whi...