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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Most answered questions in CO and Architecture

19 votes
4 answers
151
GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
State whether the following statements are TRUE or FALSE with reason:The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven...
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10 votes
4 answers
152
GATE CSE 1987 | Question: 4b
What is cache memory? What is rationale of using cache memory?
What is cache memory? What is rationale of using cache memory?
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1 votes
4 answers
154
#Set Associative Memory #computer architecture
Q. A set-associative cache consist of 60 lines,or blocks,divided into four-line sets. Main memory consist of 2K blocks of 512 works each. In the format of main memory addresses, what is the size of tag , set and word is?
Q. A set-associative cache consist of 60 lines,or blocks,divided into four-line sets. Main memory consist of 2K blocks of 512 works each. In the format of main memory add...
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3 votes
4 answers
155
UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
What will be the output at $\text{PORT1 }$if the following program is executed?MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT$37H$$82H$$B9H$$00H$
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6 votes
4 answers
158
ISRO2016-24
In which class of Flynn's taxanomy, Von Neumann architecture belongs to? SISD SIMD MIMD MISD
In which class of Flynn's taxanomy, Von Neumann architecture belongs to?SISDSIMDMIMDMISD
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2 votes
4 answers
159
immediate Addressing
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11 votes
4 answers
160
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are $\textsf{INTR & INTA}$ $\textsf{RD & WR}$ $\textsf{S0 & S1}$ $\textsf{HOLD & HLDA}$
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR & INTA}$$\textsf{RD & WR}$$\textsf{S0 & S1}$$\textsf{HOLD & HLDA}$
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7 votes
4 answers
161
ISRO2011-16
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map to does not map $6$ $11$ $54$
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map todoes not map$6$$11$$54$
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3 votes
4 answers
162
ISRO2008-37
The ability to temporarily halt the CPU and use this time to send information on buses is called direct memory access vectoring the interrupt polling cycle stealing
The ability to temporarily halt the CPU and use this time to send information on buses is calleddirect memory accessvectoring the interruptpollingcycle stealing
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6 votes
4 answers
163
ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt
An interrupt in which the external device supplies its address as well as the interrupt requests is known asvectored interruptmaskable interruptnon maskable interruptdesi...
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8 votes
4 answers
164
ISRO2007-14
The principal of the locality of reference justifies the use of virtual memory interrupts main memory cache memory
The principal of the locality of reference justifies the use ofvirtual memoryinterruptsmain memorycache memory
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7 votes
4 answers
165
ISRO2009-21, UGCNET-Dec2012-II: 12
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register? Absolute mode Indirect mode Immediate mode Index mode
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register?Absolute modeIndirect modeImmediate m...
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59 votes
4 answers
168
GATE CSE 2004 | Question: 64
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... }\\\hline \end{array} The total number of clock cycles required to execute the program is $29$ $24$ $23$ $20$
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$\begin{array}{|l|l|c|} \hline \text {Instruction} & \text...
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