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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Most answered questions in CO and Architecture

1 votes
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3682
co
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1 votes
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3683
pipeline
suppose there is unpipelined processor with a cycle time of 30ns which is evenly divided into 5 pipeline stages.The total latch latency of the pipeline will be
suppose there is unpipelined processor with a cycle time of 30ns which is evenly divided into 5 pipeline stages.The total latch latency of the pipeline will be
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1 votes
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3684
clock cycle
the maximum clock frequency at which the data path can operate is ??
the maximum clock frequency at which the data path can operate is ??
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3 votes
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3685
Differencee Between DCR and DCRL Instruction.
Want to know difference between : DCR and DCRL SUB and SUBL
Want to know difference between :DCR and DCRLSUB and SUBL
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1 votes
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3687
branch delay slot
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1 votes
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3693
DMA
https://gateoverflow.in/3547/gate2006-it_8 Arjun Sir plz anwser it.
https://gateoverflow.in/3547/gate2006-it_8Arjun Sir plz anwser it.
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1 votes
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3694
Easy one but I'm not getting Approach.
A DMA controller transfers 16Bytes to memory using cycle stealing with frequency 1.2GHz. The Number of clock cycles used for transfer of 16Bytes is 20 clock cycles. Find the throughput?
A DMA controller transfers 16Bytes to memory using cycle stealing with frequency 1.2GHz. The Number of clock cycles used for transfer of 16Bytes is 20 clock cycles. Find ...
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3696
Finding Control memory address register if cpi and instruction counter is given
Also, memory address bit is given. Control memory address register and control memory data register are to find.
Also, memory address bit is given. Control memory address register and control memory data register are to find.
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3697
please see it once
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