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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Most answered questions in CO and Architecture

13 votes
5 answers
93
ISRO2015-77
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it? $4$ $6$ $8$ $10$
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it?$4$$6$$8$$10$
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12 votes
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95
ISRO2014-1
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for additional circuitry like buffering and decoding. $0$ $1$ $2$ $3$
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for addition...
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70 votes
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96
GATE CSE 2015 Set 3 | Question: 51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$.$$\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline...
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36 votes
5 answers
102
GATE CSE 1996 | Question: 26
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below:$$\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = ...
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33 votes
5 answers
108
GATE CSE 1998 | Question: 18
For a set-associative Cache organization, the parameters are as follows: ... $1 \leq m \leq l$. Give the value of the hit ratio for $l = 1$.
For a set-associative Cache organization, the parameters are as follows:$$\begin{array}{|c|l|} \hline \text {$t _c$} & \text{Cache Access Time }\\\hline \text{$t _m$} &...
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