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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Previous GATE Questions in CO and Architecture

25 votes
3 answers
121
16 votes
2 answers
123
Which of the following statements is true?ROM is a Read/Write memoryPC points to the last instruction that was executedStack works on the principle of LIFOAll instruction...
1 votes
1 answer
124
22 votes
2 answers
127
State True or False with one line explanationExpanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.
35 votes
3 answers
133
3 votes
1 answer
134
Contents of A register after the execution of the following 8085 microprocessor program is MVIA, 55 H MVI C, 25 H ADDC DAA 7AH80H50H22H
16 votes
3 answers
135
The correct matching for the following pairs is:$$\begin{array}{ll} \text{(A) DMA I/O} & \text{(1) High speed RAM} \\ \text{(B) Cache} & \text{(2) Disk} \\ \text{(C) I...
1 votes
1 answer
136