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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Previous GATE Questions in CO and Architecture

29 votes
3 answers
62
GATE CSE 1989 | Question: 2-ii
Match the pairs in the following questions: ...
Match the pairs in the following questions:$$\begin{array}{ll|ll}\hline \text{(A)} & \text{Base addressing} & \text{(p)} & \text{Reentranecy} \\\hline \text{(B)} & \text...
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4 votes
0 answers
65
GATE CSE 1990 | Question: 4-iv
State whether the following statements are TRUE or FALSE with reason: Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate at its maximum speed.
State whether the following statements are TRUE or FALSE with reason:Transferring data in blocks from the main memory to the cache memory enables an interleaved main memo...
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9 votes
3 answers
66
GATE CSE 1990 | Question: 4-iii
State whether the following statements are TRUE or FALSE with reason: The flags are affected when conditional CALL or JUMP instructions are executed.
State whether the following statements are TRUE or FALSE with reason:The flags are affected when conditional CALL or JUMP instructions are executed.
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19 votes
4 answers
67
GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
State whether the following statements are TRUE or FALSE with reason:The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven...
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10 votes
4 answers
69
GATE CSE 1987 | Question: 4b
What is cache memory? What is rationale of using cache memory?
What is cache memory? What is rationale of using cache memory?
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2 votes
3 answers
71
GATE CSE 1987 | Question: 2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.
State whether the following statements are TRUE or FALSE:Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/...
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5 votes
3 answers
72
GATE CSE 1987 | Question: 2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
State whether the following statements are TRUE or FALSEIn a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the micro...
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3 votes
1 answer
73
GATE CSE 1987 | Question: 1-ix
The refreshing rate of dynamic RAMs is in the range of $2$ microseconds $2$ milliseconds. $50$ milliseconds $500$ milliseconds
The refreshing rate of dynamic RAMs is in the range of$2$ microseconds$2$ milliseconds.$50$ milliseconds$500$ milliseconds
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45 votes
6 answers
76
GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode
The most relevant addressing mode to write position-independent codes is:Direct modeIndirect modeRelative modeIndexed mode
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8 votes
1 answer
77
GATE CSE 1990 | Question: 4-iv
Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.True/False.Explain.
Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.True/False.Explain.
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59 votes
4 answers
80
GATE CSE 2004 | Question: 64
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... }\\\hline \end{array} The total number of clock cycles required to execute the program is $29$ $24$ $23$ $20$
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$\begin{array}{|l|l|c|} \hline \text {Instruction} & \text...
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