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$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline \textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum} \\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2 \\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5 \\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline \end{array}}}$$

Hot questions in CO and Architecture

1
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB ... average instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
2
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... is taken during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$
3
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register read ... clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
4
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access ... $10$ times. The number of conflict misses experienced by the cache is _________ .
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$. $\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline & \text{1}& \text{2} & \text{$3$} & \text{$4$} & \text{$5$} \\\hline \textbf{$S _1$} & \text{$ ... $}\\\hline \textbf{$S _3$} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______
Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$uses indirect addressing mode.$A$and$B$are memory addresses ... destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is:$3456$56 votes 8 answers 8 The stage delays in a$4$-stage pipeline are$800, 500, 400$and$300$picoseconds. The first stage (with delay$800$picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays$600$and$350$picoseconds. The throughput increase of the pipeline is ___________ percent. 35 votes 5 answers 9 Consider a system with$2$level cache. Access times of Level$1$cache, Level$2$cache and main memory are$1ns$,$10ns$, and$500ns$respectively. The hit rates of Level$1$and Level$2$caches are$0.8$and$0.9$, respectively. What is the average access time of the system ignoring the search time within the cache?$13.012.812.612.4$62 votes 10 answers 10 Consider a machine with a byte addressable main memory of$2^{16}$bytes. Assume that a direct mapped data cache consisting of$32$lines of$64bytes$each is used in the system. A$50$x$50$two-dimensional array of bytes is stored in the main memory starting from ... of the data cache do not change in between the two accesses. How many data misses will occur in total?$48505659$66 votes 9 answers 11 Consider a two-level cache hierarchy with$L1$and$L2$caches. An application incurs$1.4$memory accesses per instruction on average. For this application, the miss rate of$L1$cache is$0.1$; the$L2$cache experiences, on average,$7$misses per$1000$instructions. The miss rate of$L2$expressed correct to two decimal places is ________. 76 votes 10 answers 12 Suppose the functions$F$and$G$can be computed in$5$and$3$nanoseconds by functional units$U_{F}$and$U_{G}$, respectively. Given two instances of$U_{F}$and two instances of$U_{G}$, it is required to implement the computation$F(G(X_{i}))$for$1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds. 42 votes 5 answers 13 A processor has$16$integer registers$(R0, R1, \ldots , R15)$and$64$floating point registers$(F0, F1, \ldots , F63).$It uses a$2- byte$instruction format. There are four categories of instructions:$Type-1, Type-2, Type-3,$and$Type-4.Type-1$...$Type-4$category consists of$N$instructions, each with a floating point register operand$(1F).$The maximum value of$N$is _____ 56 votes 5 answers 14 A computer system has an$L1$cache, an$L2$cache, and a main memory unit connected as shown below. The block size in$L1$cache is$4$words. The block size in$L2$cache is$16$words. The memory access times are$2 \hspace{0.1cm} nanoseconds$... this transfer?$2 \hspace{0.1cm} nanoseconds20 \hspace{0.1cm} nanoseconds22 \hspace{0.1cm}nanoseconds88 \hspace{0.1cm} nanoseconds$42 votes 3 answers 15 In a two-level cache system, the access times of$L_1$and$L_2$caches are$1$and$8$clock cycles, respectively. The miss penalty from the$L_2$cache to main memory is$18$clock cycles. The miss rate of$L_1$cache is twice that of$L_2$. The average memory access time (AMAT) of ... and$L_2$respectively are$0.111$and$0.0560.056$and$0.1110.0892$and$0.17840.1784$and$0.0892$16 votes 3 answers 16 I want to clearly understand the difference between compulsory miss, conflict miss and capacity miss what I understood is compulsory miss: when a block of main memory is trying to occupy fresh empty line of cache, it is called compulsory miss conflict miss: when ... set-associative cache. Because in associative mapping, no block of main memory tries to occupy already filled line. is this correct? 77 votes 6 answers 17 An access sequence of cache block addresses is of length$N$and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by$k$. What is the miss ratio if the access sequence is passed through a cache of ...$\left(\dfrac{1}{N}\right)\left(\dfrac{1}{A}\right)\left(\dfrac{k}{n}\right)$6 votes 2 answers 18 .. 34 votes 6 answers 19 The instruction pipeline of a RISC processor has the following stages: Instruction Fetch$(IF)$, Instruction Decode$(ID)$, Operand Fetch$(OF)$, Perform Operation$(PO)$and Writeback$(WB)$, The$IF$,$ID$,$OF$and$WB$stages take$1$... there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____. 42 votes 10 answers 20 A cache memory unit with capacity of$N$words and block size of$B\$ words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ____________ bits.