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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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41 votes
11 answers
205
GATE CSE 2006 | Question: 09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?$400$$500...
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29 votes
3 answers
206
GATE CSE 1989 | Question: 2-ii
Match the pairs in the following questions: ...
Match the pairs in the following questions:$$\begin{array}{ll|ll}\hline \text{(A)} & \text{Base addressing} & \text{(p)} & \text{Reentranecy} \\\hline \text{(B)} & \text...
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0 votes
1 answer
207
Cache Mapping
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the cache is 16 Bytes, then average memory access time including miss penalty is?
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the...
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0 votes
2 answers
208
gate at zeal
What is smallest negative value expressed in 8 bit 2 complement from that when added to itself, the sum causes an overflow?
What is smallest negative value expressed in 8 bit 2 complement from that when added to itself, the sum causes an overflow?
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0 votes
1 answer
211
COA DMA
Consider a device operating on 8MBPS speed and tranferring the data to memory using cycle stealing mode of DMA.If it takes 250nsec to tranfer 16 bytes data to memory when it is ready/prepared.Then the percentage of time CPU is blocked due to DMA is?
Consider a device operating on 8MBPS speed and tranferring the data to memory using cycle stealing mode of DMA.If it takes 250nsec to tranfer 16 bytes data to memory when...
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0 votes
0 answers
212
Hit Latency | Computer Organization
is this formula is correct if it is correct then in gate 2006 Question 75 why they not used this formula https://gateoverflow.in/43565/gate-cse-2006-question-75
is this formula is correct if it is correct then in gate 2006 Question 75 why they not used this formulahttps://gateoverflow.in/43565/gate-cse-2006-question-75
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0 votes
0 answers
218
Self Doubt Random found on Internet
Consider a system which supports 2-address and 1-address instructions both. System has 20-bits instructions and 7-bits addresses then which of the following is/are the number of 1-address instructions possible for the system?
Consider a system which supports 2-address and 1-address instructions both. System has 20-bits instructions and 7-bits addresses then which of the following is/are the nu...
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6 votes
5 answers
219
ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ different implementations of the fo...
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0 votes
2 answers
220
Addressing mode
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