Register

Web Page

Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Filter

Hot questions in CO and Architecture

0 votes
1 answer
221
IB JIO II Tech 2023
What is capacity of memory having 16 address lines of row decoder, 8 address lines for column decoder and 8 data lines? 1. 4MB 2. 16MB 3. 8MB 4. 32MB
What is capacity of memory having 16 address lines of row decoder, 8 address lines for column decoder and 8 data lines?1. 4MB 2. 16MB 3. 8MB 4. 32MB
User Avatar
0 votes
1 answer
223
Unacadmey book
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non pipeline processor.
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non ...
User Avatar
44 votes
5 answers
228
GATE CSE 2001 | Question: 1.7, ISRO2008-18
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above
More than one word are put in one cache block to:exploit the temporal locality of reference in a programexploit the spatial locality of reference in a programreduce the m...
User Avatar
2 votes
1 answer
229
NTRO EXAM
In a pipeline with three stages, what is the minimum number of instructions that must be in the pipeline to achieve maximum speedup? A) 1 B) 2 C) 3 D) 4
In a pipeline with three stages, what is the minimum number of instructions thatmust be in the pipeline to achieve maximum speedup?A) 1 ...
User Avatar
3 votes
4 answers
231
UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
What will be the output at $\text{PORT1 }$if the following program is executed?MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT$37H$$82H$$B9H$$00H$
User Avatar
40 votes
4 answers
232
GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing
Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relat...
User Avatar
42 votes
2 answers
234
GATE IT 2006 | Question: 42
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is: $32$ $ns$ $64$ $ns$ $96$ $ns$ $128$ $ns$
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is:$...
User Avatar
1 votes
2 answers
236
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is$625$ line...
User Avatar
0 votes
1 answer
239
Computer Organization
Under what category does Universal Serial Bus fall: System Bus or a Network connection or something else?
Under what category does Universal Serial Bus fall: System Bus or a Network connection or something else?
User Avatar
6 votes
3 answers
240
ISRO2020-46
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes? $1,280,000$ $1280$ $1250$ $128,000$
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes?$1,...
User Avatar
Page: