Register

Web Page

Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Filter

Hot questions in CO and Architecture

0 votes
0 answers
302
Calcutta University Question Paper
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MALS 0 1 2 3 4 S1 A B A B S2 A A S3 B AB A
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MA...
User Avatar
0 votes
1 answer
303
Gate@Zeal 2022
Answer 1.03
Answer 1.03
User Avatar
0 votes
2 answers
304
Gate@Zeal 2022 Test Series
Answer 1.18
Answer 1.18
User Avatar
0 votes
0 answers
306
COA Doubt
What is the bandwidth of the memory , if access time and settling time of main memory are 45 ns and 5 ns respectively ? 20 Hz 20 KHz 20 MHz 50 MHZ
What is the bandwidth of the memory , if access time and settling time of main memory are 45 ns and 5 ns respectively ? 20 Hz20 KHz20 MHz50 MHZ
User Avatar
40 votes
3 answers
307
GATE IT 2006 | Question: 40
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ ... value $20$ Memory location $1020$ has value $20$ Memory location $1021$ has value $20$ Memory location $1001$ has value $20$
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ respectively before the following program is executed.$$\begin{array}{ll} \text{MOVI} & \text...
User Avatar
5 votes
1 answer
308
Carl Hamacher
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.What is the Effective address of the memory operand in each of the following instructions? a) Load 20(R1),R5 b) Move #3000,R5 c) Store R5,30(R1,R2) d) Add -(R2),R5 e) Subtract (R1)+,R5
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.What is the Effectiveaddress of the memory operand in each of the following instructions?a) Loa...
User Avatar
0 votes
3 answers
309
Average Memory Access Time Problem
A cache is having 60% hit ratio for read operation. Cache access time is 30 ns and main memory access time is 100 ns, 50% operations are read operation. What will be the average access time for read operation? (a) 50 ns (b) 58 ns (c) 100 ns (d) 70 ns
A cache is having 60% hit ratio for read operation. Cache access time is 30 ns and main memory access time is 100 ns, 50% operations are read operation. What will be the ...
User Avatar
0 votes
2 answers
310
co control word
Q:- micro programmed CU supports 400 control signals micro instruction is designed in such a way that 4 signals are active . What is the size of a control field in the instruction ?
Q:- micro programmed CU supports 400 control signals micro instruction is designed in such a way that 4 signals are active . What is the size of a control field in the ...
User Avatar
0 votes
1 answer
311
instruction-format
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then how many two instructions are possible at maximum?
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then ho...
User Avatar
2 votes
1 answer
313
cache memory
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of 32 bytes each organized as directed mapped The size of Main memory is __ Mbytes?
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of...
User Avatar
Page: