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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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1 votes
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3361
Identify the correct option?
For which register, the effective register (BX) EA=(DI) is (SI) a) relative base indexed b)register indirect c)base indexed d)register relative
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Cache memory access time
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CO 2001
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3371
doubt regarding Addressing mode
Can someone explain this line in simple words. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.
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3372
Can any one plz solve this basic gate circuit question
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3374
Floating Point Arithmetic
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3375
Computer Organization Question
A computer with 32-bit wide data bus uses 4 K x 8 static RAM memory chips. The smallest memory this computer can have is: (a) 32 kb (b) 16 kb (c) 8 kb (d) 24 kb
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CS-ISRO-2011-25
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3380
tlb
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