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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Hot questions in CO and Architecture

4 votes
2 answers
3482
cache
how many comparator and multiplexer are required in set assosiative maping technique . ?? what i know till now is if it is p way set assosiative then p comparator will be required.. how many multiplexer will be required. ?
how many comparator and multiplexer are required in set assosiative maping technique . ?? what i know till now is if it is p way set assosiative then p comparator will be...
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0 votes
1 answer
3486
pc increment in cisc instructions
When is incremented value of PC(program counter) available in variable sized instructions? during decode phase after instruction execution during fetch phase none
When is incremented value of PC(program counter) available in variable sized instructions?during decode phaseafter instruction executionduring fetch phasenone
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0 votes
1 answer
3490
Consider 1 Ghz clock frequency processor , uses different operand accessing models shown below
My question is : in the last indexed instruction , will it not be this way : 1 Memory Access + 1 Arithmetic computation + 1 Memory access = 2 + 3 + 2 = 7 clock cycles ?
My question is : in the last indexed instruction , will it not be this way :1 Memory Access + 1 Arithmetic computation + 1 Memory access = 2 + 3 + 2 = 7 clock cycles ?
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1 votes
1 answer
3492
Max size of main memory
why this qs has no effect of two level paging??i dont know if the answer given by madeeasy is right..
why this qs has no effect of two level paging??i dont know if the answer given by madeeasy is right..
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0 votes
1 answer
3498
minimum no. of tables required in M:N relationship among 2 entity sets satisfying 3NF
if there is one to many relationship from entity set A to B; B has simple primary key and a multivalued attribute, then min no. of tables satisfying 3NF?
if there is one to many relationship from entity set A to B; B has simple primary key and a multivalued attribute, then min no. of tables satisfying 3NF?
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2 votes
3 answers
3499
What is the answer ?
Suppose that a cache is 20 times faster than main memory and cache memory can be used 80% of the time. The speed-up factor that can be achieved by using the cache is _________.
Suppose that a cache is 20 times faster than main memory and cache memory can be used 80% of the time. The speed-up factor that can be achieved by using the cache is ____...
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0 votes
1 answer
3500
Micro INSTRUCTION
In Horizontal Micro Programming ONE Operation is executed in ONE Clock Cycle In Vertical Micro Programming , IN one clock cycle ______ operations are executed ONE log2 N
In Horizontal Micro Programming ONE Operation is executed in ONE Clock CycleIn Vertical Micro Programming , IN one clock cycle ______ operations are executedONElog2 N
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