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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Hot questions in CO and Architecture

5 votes
4 answers
1
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ bytes. Consider the following four physical addresses represented in hexadecimal notation. $A1= 0x42C8A4$ ... same cache set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.
asked Feb 12 in CO and Architecture Arjun 1.8k views
40 votes
3 answers
2
Which of the following statements about relative addressing mode is FALSE? It enables reduced instruction size It allows indexing of array element with same instruction It enables easy relocation of data It enables faster address calculation than absolute addressing
asked Oct 31, 2014 in CO and Architecture Ishrat Jahan 6.3k views
50 votes
7 answers
3
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is completed. Under ... , and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.
asked Sep 14, 2014 in CO and Architecture Kathleen 6.3k views
12 votes
6 answers
4
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
asked Feb 14, 2018 in CO and Architecture gatecse 4.2k views
21 votes
4 answers
5
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.
asked Sep 22, 2014 in CO and Architecture Kathleen 7.3k views
21 votes
4 answers
6
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____
asked Sep 28, 2014 in CO and Architecture jothee 10.4k views
3 votes
6 answers
7
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of execution of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$
asked Feb 12 in CO and Architecture Arjun 1.5k views
10 votes
3 answers
8
Can anyone explains when to use this formulas? Average memory access time (AMAT) AMAT = Hit Time + Miss Rate * Miss Penality OR • Effective Access Time: 1. Hit Rate * Hit time+ Miss Rate * Miss Penality 2. [ (H)(TLB access time + mem access time) + (1-H)(TLB access + PT access + mem access)]
asked Jan 17, 2016 in CO and Architecture Pradip Nichite 17.1k views
33 votes
6 answers
9
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: before effective address calculation has started during effective address calculation after effective address calculation has completed after data cache lookup has completed
asked Sep 12, 2014 in CO and Architecture Kathleen 5.8k views
29 votes
5 answers
10
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above
asked Sep 14, 2014 in CO and Architecture Kathleen 6.5k views
21 votes
9 answers
11
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is _______
asked Feb 14, 2017 in CO and Architecture Madhav 4.3k views
11 votes
5 answers
12
Consider a 33MHz cpu based system. What is the number of wait states required if it is interfaced with a 60ns memory? Assume a maximum of 10ns delay for additional circuitry like buffering and decoding. 0 1 2 3
asked Sep 8, 2015 in CO and Architecture ajit 6.3k views
6 votes
5 answers
13
How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory. $5.27$ $2.00$ $4.16$ $6.09$
asked Apr 26, 2016 in CO and Architecture makhdoom ghaya 5.7k views
7 votes
6 answers
14
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 $\times$ 6 array, where each chip is 8K $\times$ 4 bits ? 13 15 16 17
asked Aug 15, 2015 in CO and Architecture ajit 6k views
22 votes
4 answers
15
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$
asked Sep 22, 2014 in CO and Architecture Kathleen 6.4k views
29 votes
2 answers
16
Register renaming is done in pipelined processors: as an alternative to register allocation at compile time for efficient access to function parameters and local variables to handle certain kinds of hazards as part of address translation
asked Aug 5, 2014 in CO and Architecture gatecse 6.2k views
27 votes
3 answers
17
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: $\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = $ ... access time of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?
asked Oct 10, 2014 in CO and Architecture Kathleen 5k views
24 votes
2 answers
18
Consider the following assembly language program for a hypothetical processor $A, B,$ and $C$ are $8-$bit registers. The meanings of various instructions are shown as comments. $\begin{array}{lll} & \text{MOV B, #0}&& \text{;} & \text{$ ... of register B after the program execution will be the number of $0$ bits in $A_0$ the number of $1$ bits in $A_0$ $A_0$ $8$
asked Sep 17, 2014 in CO and Architecture Kathleen 5.9k views
35 votes
4 answers
19
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. ... cycles needed to execute the above code segment assuming each instruction takes one cycle to execute? $7$ $10$ $13$ $14$
asked Oct 30, 2014 in CO and Architecture Ishrat Jahan 6k views
28 votes
6 answers
20
Suppose a processor does not have any stack pointer registers, which of the following statements is true? It cannot have subroutine call instruction It cannot have nested subroutines call Interrupts are not possible All subroutine calls and interrupts are possible
asked Sep 14, 2014 in CO and Architecture Kathleen 6k views
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