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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline

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asked Sep 24, 2018 in CO and Architecture by Na462 Loyal (6.9k points) | 232 views
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asked Dec 12, 2018 in CO and Architecture by Soumya Tiwari Active (2.2k points) | 24 views
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