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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Most viewed questions in CO and Architecture

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3361
PL output of function
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3 votes
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3362
ME FLT-2
i got 0.092ns but how it is 92MIPS?
i got 0.092ns but how it is 92MIPS?
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1 answer
3363
Self-doubt
What is actually meant by average access time experienced by processor?
What is actually meant by average access time experienced by processor?
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3366
Gate 2012 MUX problem
What is the answer and how ?
What is the answer and how ?
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1 votes
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3367
branch delay slot
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3370
self doubt
Which addressing mode is best suited for runtime relocation. Which addressing mode is best suited for compile time relocation.
Which addressing mode is best suited for runtime relocation.Which addressing mode is best suited for compile time relocation.
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3371
Semester exam
1) A two way set associative cache memory uses a block size of 4 words . The cache can accommodate a total of 2048 words from main memory. The main memory size is 128kx32. a) What is the size of the cache memory.
1) A two way set associative cache memory uses a block size of 4 words . The cache canaccommodate a total of 2048 words from main memory. The main memory size is128kx32.a...
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3372
assembly
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3373
DIRECT CACHE
https://gateoverflow.in/863/gate2002-10 IN THE SOLUTION BY ARJUN SIR HOW THIS LINE IS JUSTIFYING THAT ALL WILL MAP TO DIFFERENT SET?????? So, since the ending address is not extending beyond these 9 bits,9 bits, all cache accesses are to diff sets.
https://gateoverflow.in/863/gate2002-10IN THE SOLUTION BY ARJUN SIR HOW THIS LINE IS JUSTIFYING THAT ALL WILL MAP TO DIFFERENT SET?????? So, since the ending address is n...
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3374
Pipeline organization
Please give detailed answer if possible please draw diagram
Please give detailed answer if possible please draw diagram
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3376
Prove using boolean diagram.
(ABC)'=A'+B'+C'
(ABC)'=A'+B'+C'
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3378
Interrupts
If Some device wants to Transfer some bytes into memory ?? .. By using which signal the Device will contact the CPU?? READY[I am ready to transfer] Or INTR
If Some device wants to Transfer some bytes into memory ?? ..By using which signal the Device will contact the CPU??READY[I am ready to transfer] OrINTR
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3379
#Cache Memory
For next three question consider a 32 byte 2-way set associative cache with 4-byte cache blocks and LRU replacement policy. Following addresses (written in decimal) in the following order on an initially empty cache: 0,16,32,2,14,34,12,20,36 1) Capacity miss 2) Compulsory miss 3) Conflict miss
For next three question consider a 32 byte 2-way set associative cache with 4-byte cache blocks and LRU replacement policy. Following addresses (written in decimal) in th...
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3380
Avg. Access Time
When we calculate avg access time, If it is not given in question like it is Hierarchal or Simultaneous access then by default we have to take which access to calculate avg access time?
When we calculate avg access time, If it is not given in question like it is Hierarchal or Simultaneous access then by default we have to take which access to calculate a...
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