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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Highest voted questions in CO and Architecture

27 votes
3 answers
151
GATE CSE 1988 | Question: 2-ii
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer. ...
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer...
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27 votes
1 answer
154
GATE CSE 2005 | Question: 66
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. ... $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$$\begin{array...
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25 votes
3 answers
158
GATE CSE 1995 | Question: 1.6
The principle of locality justifies the use of: Interrupts DMA Polling Cache Memory
The principle of locality justifies the use of:InterruptsDMAPollingCache Memory
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24 votes
3 answers
163
GATE CSE 2005 | Question: 67
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and ...
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24 votes
2 answers
164
GATE CSE 2009 | Question: 29
Consider a $4$-way set associative cache (initially empty) with total $16$ cache blocks. The main memory consists of $256$ ... $3$ $8$ $129$ $216$
Consider a $4$-way set associative cache (initially empty) with total $16$ cache blocks. The main memory consists of $256$ blocks and the request for memory blocks are in...
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23 votes
4 answers
167
GATE CSE 2016 Set 1 | Question: 09
A processor can support a maximum memory of $4\;\textsf{GB}$, where the memory is word-addressable (a word consists of two bytes). The size of address bus of the processor is at least _________bits.
A processor can support a maximum memory of $4\;\textsf{GB}$, where the memory is word-addressable (a word consists of two bytes). The size of address bus of the processo...
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23 votes
2 answers
168
GATE CSE 1995 | Question: 2.25
A computer system has a $4 \ K$ word cache organized in block-set-associative manner with $4$ blocks per set, $64$ words per block. The number of bits in the SET and WORD fields of the main memory address format is: $15, 40$ $6, 4$ $7, 2$ $4, 6$
A computer system has a $4 \ K$ word cache organized in block-set-associative manner with $4$ blocks per set, $64$ words per block. The number of bits in the SET and WORD...
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23 votes
4 answers
169
GATE CSE 2002 | Question: 1.9
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while: $\overline{INTA}$ is active HOLD is active READY is inactive None of the above
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:$\overline{INTA}$ is activeHOLD is activeREADY is inactiveNone of the ab...
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