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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Highest voted questions in CO and Architecture

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3363
techtud
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address sp...
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3365
interrupt
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3366
TEST_SERIES
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3367
gate 2005
How is I/O protection ensured by CPU having isolated mapped I/O?
How is I/O protection ensured by CPU having isolated mapped I/O?
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3368
techtud
In a two level memory hierarchy, the access time of cache memory is 12 ns and the access time of the main memory is 1500 ns. The hit ratio is 0.98, the average access time of two-level memory system is (A) 44.05 ns (B) 41.76 ns (C) 46.94 ns (D) 40.25 ns
In a two level memory hierarchy, the access time of cache memory is 12 ns and the access time of the main memory is 1500 ns. The hit ratio is 0.98, the average access tim...
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3369
Made Easy CO
Suppose that in 1000 memory references there are 40 misses in L1 and 20 misses in L2 cache. Assume miss penalty from L2 to memory is 100 cycles. The hit time of L2 is 10 clock cycles. The hit time of L1 is 1 clock cycle. What is the average memory access time ?
Suppose that in 1000 memory references there are 40 misses in L1 and 20 misses in L2 cache. Assume miss penalty from L2 to memory is 100 cycles. The hit time of L2 is 10 ...
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3370
IBPS SO
What does processor speed depend upon? 1)Clock 2)Data bus width 3)Address bus width 4)All of the above
What does processor speed depend upon?1)Clock2)Data bus width3)Address bus width4)All of the above
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3371
NUmber of cycles in pipeline
I am getting 15 as the answer.
I am getting 15 as the answer.
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3374
# CO Dout
1 word is equal to how many bytes or is there is way to calculate from given scenario??
1 word is equal to how many bytes or is there is way to calculate from given scenario??
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3375
explain
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3376
polling
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3378
GATE CSE 1988 | Question: 5ii
Briefly explain the term “Configuring a programmable peripheral chip”.
Briefly explain the term “Configuring a programmable peripheral chip”.
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