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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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181
Interrupts
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If Some device wants to Transfer some bytes into memory ?? ..By using which signal the Device will contact the CPU??READY[I am ready to transfer] OrINTR
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182
Computer Organization and Architecture
Please clarify the fourth option only. My doubt: if the same word in requires repeatedly, then for the first the word will be miss and there after it is continuously in use how it can be miss.
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183
Computer Organization and Architecture
While calculating the average read time , why 0.9*10 + 0.1*(10+110) is not used. .i.e. why cache time is not added in miss frequency.
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184
Gate@Zeal 2022
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186
Computer organization and architecture
1. In memory hierarchy the fattest memory type is cache memory next to register. So describe mapping process(transformation data from memory to cache memory)
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187
Vishvadeep sir DPP, Instructions
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190
Basic COA
Why ALU can’t accept operand directly from input/output devices ?
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193
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Is Daisy chaining following Non-vectored interrupt protocol ??. I
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196
#Expanding opcode
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197
Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??
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200
In a pipelined architecture Static branch prediction is used with branch taken assumption. Assume that 30% of the instructions executed for a program are branch instructions. Each stage has 2 nsec delay. Average Execution time(in nsec) if 80 % of the instructions are taken?
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