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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

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202
Accesing time
Could you please differentiate below . Memory access time .hit time . search time ?? Arey yar some one answer this.. why so dumb
Could you please differentiate below. Memory access time.hit time. search time??Arey yar some one answer this.. why so dumb
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1 answer
203
#addressing modes
How to implement indirect addressing mode using register indirect addressing mode???
How to implement indirect addressing mode using register indirect addressing mode???
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0 answers
204
#conflict misses
Fully associative cache yields no conflict misses?? Or yields very very very very less conflict misses
Fully associative cache yields no conflict misses?? Or yields very very very very less conflict misses
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207
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of 500
Quantify the effect on performance that results from the use of a cache in the case of a program that has a total of 500 instructions, including a 100-instruction loop th...
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2 votes
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208
Addressing modes
Could you please explain How we can implement indirect addressing mode using Index addressing mode.. and vice versa..??
Could you please explain How we can implement indirect addressing mode using Index addressing mode.. and vice versa..??
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209
ISA architrecture
Write a stack-based program that computes the following function : 5+(3x7) – 8, assuming that the stack starts out empty
Write a stack-based program that computes the following function : 5+(3x7) – 8, assuming that the stack starts out empty
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212
Both internal and software interrupts are same ? Example : system call
Both internal and software caused by executing the program instructions . So both are same ?
Both internal and software caused by executing the program instructions . So both are same ?
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213
Pipeline Architecture
if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the pipeline? how about if the processor is divided into 50 pipeline stages?
if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the ...
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215
Program runs in 100s . Multiplies 80 % of program . Designer M can improve speedup of multiply operations . Now , I am a user and I need to make MY program 5 times faster . How much speedup of multiply instructions should M achieve to allow me to reach my overall speedup goal ?
The program runs in 100s. Multiplies 80 % of the program. Designer M can improve the speedup of multiply operations. Now, I am a user and I need to make MY program 5 time...
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1 votes
1 answer
216
Consider a system which supports only 1-address type instructions. The size of memory the system has is 2^m KB. The system supports ' i ' distinct instructions. The length of an instruction is ____ Bytes?
Consider a system which supports only 1-address type instructions. The size of memory the system has is $2^m$ KB. The system supports ' i ' distinct instructions. The len...
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2 votes
0 answers
219
A system is based on an 8-bit microprocessor and has two I/O devices. The I/O controllers for this system use separate control and status registers.
A system is based on an 8-bit microprocessor and has two I/O devices. The I/O controllers for this system use separate control and status registers. Both devices handle d...
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2 answers
220
can 0 address instruction be used in accumulator based architecture? how?
In 0-address instruction, no address is specified within an instruction along with the Opcode, so is it possible to use 0-address instruction in accumulator based architecture?
In 0-address instruction, no address is specified within an instruction along with the Opcode, so is it possible to use 0-address instruction in accumulator based archite...
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