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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

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1 answer
2161
Testbook Test Series: CO & Architecture - Cache Memory
If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets, How big is the cache in Megabytes ?
If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets,How big is the cache in Megabytes ?
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0 answers
2162
Block replacement in cache
How we replace blocks in k-way set associative cache ? What strategy we follow?
How we replace blocks in k-way set associative cache ? What strategy we follow?
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0 votes
0 answers
2163
Peripheral devices : CAO
Consider READ and WRITE bits: a) Both are written by CPU b) Both are written by peripheral c) READ bit is written by peripheral while WRITE bit is written by CPU d) WRITE bit is written by peripheral while READ bit is written by CPU
Consider READ and WRITE bits:a) Both are written by CPUb) Both are written by peripheralc) READ bit is written by peripheral while WRITE bit is written by CPUd) WRITE bit...
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1 votes
1 answer
2164
Implementation of OR gate using multiplexer.
How we implement OR gate using 2-to-1 multiplexer?
How we implement OR gate using 2-to-1 multiplexer?
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2 votes
1 answer
2165
Miss rate and miss penalty
Difference in miss rate and miss panelaty ?
Difference in miss rate and miss panelaty ?
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1 votes
1 answer
2166
DM controller
What is the difference between DM controller and micropcessor. Block diagram of the device seems similar , both contains pins. Then how they are different from each other?
What is the difference between DM controller and micropcessor. Block diagram of the device seems similar , both contains pins. Then how they are different from each other...
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0 votes
1 answer
2167
Performance consideration from coa
How this average access time derived ? Tavg=hC+(1-h)M. Please explain. M not getting this.
How this average access time derived ?Tavg=hC+(1-h)M.Please explain. M not getting this.
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1 votes
1 answer
2168
LRU_page replacement algorithm.
How LRU page replacement algorithm works? I am unable to visualize it from book hamacher. Please anyone explain in simple language.
How LRU page replacement algorithm works? I am unable to visualize it from book hamacher. Please anyone explain in simple language.
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2 votes
1 answer
2169
Coa-cache memory.
Cache size = 512KB ; Tag size = 7, Find out main memory size and tag directory. Given it is 8-way set associative .
Cache size = 512KB ; Tag size = 7, Find out main memory size and tag directory. Given it is 8-way set associative .
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0 votes
1 answer
2171
Internal organization of memory chip.
What are external connection in "internal organization of memory chip" ? How these lines are decided ? Example memory with 128 bits (16×8) requires 14 external connections. How we decided this ☝ ?
What are external connection in "internal organization of memory chip" ? How these lines are decided ?Example memory with 128 bits (16×8) requires 14 external connection...
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0 votes
1 answer
2172
One bit data and one bit information are same ?
Some times it is given that memory cell stores one bit of information and some times one bit of data. Are these two statements same ? Register store one bit of data and memory cell stores one bit if information ? Difference in two ?
Some times it is given that memory cell stores one bit of information and some times one bit of data. Are these two statements same ?Register store one bit of data and me...
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0 votes
1 answer
2173
Address generated by CPU is dependent on which factor?
Does address sent by CPU to Main Memory varies according to size of processor? 32 bit computer means size of processor or can it send 32 bits in one address to memory. Explain about address length sent by CPU
Does address sent by CPU to Main Memory varies according to size of processor? 32 bit computer means size of processor or can it send 32 bits in one address to memory. ...
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0 votes
1 answer
2175
Measurement of performance of computer system
Response time, elapsed time, access time all are consider same and equivalent ? Explanation.
Response time, elapsed time, access time all are consider same and equivalent ? Explanation.
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0 votes
1 answer
2176
Doubt from coa. How bus length is decided?
Bus width is depends on word length of computer ? If computer is having 32 bit memory I.e. 4 byte = one word. So, bus length will be 4 ?
Bus width is depends on word length of computer ? If computer is having 32 bit memory I.e. 4 byte = one word. So, bus length will be 4 ?
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1 votes
2 answers
2177
ISI-JRF
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
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0 votes
1 answer
2178
Computer Organization- Memory Addressing
For 16 bit address-bus, if an 8 K RAM chip is selected when $A_{13}, A_{14}$ and $A_{15}$ address bits are all one, then what is the range of the memory address? Options - a) 2 b) 3 c) 4 d) 5
For 16 bit address-bus, if an 8 K RAM chip is selected when $A_{13}, A_{14}$ and $A_{15}$ address bits are all one, then what is the range of the memory address?Options -...
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0 votes
2 answers
2179
morris mano
why indirect addressing mode has large address space
why indirect addressing mode has large address space
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0 votes
1 answer
2180
program-status-word, computer-architecture
What are the various values of Carry(C), Overflow (V) and Sign (S) flag in case of signed unsigned, 2's complement addition and subtraction. When are they set to 0 / 1 and what do they mean ?
What are the various values of Carry(C), Overflow (V) and Sign (S) flag in case of signed unsigned, 2's complement addition and subtraction. When are they set to 0 / 1 an...
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