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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

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242
Self doubt
Can each operand have a separate mode in a double operand instruction?
Can each operand have a separate mode in a double operand instruction?
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1 votes
0 answers
244
Applied Test Series
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with a tag field in the address of 9 bits. The total number of cache lines/ blocks in the cache are_____
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size. Assume a four-way set-associative cache with...
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1 answer
245
Testbook test series
Can anyone please solve this?
Can anyone please solve this?
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3 answers
248
Applied Test Series:
Need help Anyone?
Need help Anyone?
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1 votes
1 answer
250
Applied Test Series
Consider the following sequence of instructions Add #20,R0,R1 Mul #3,R2,R3 And # ... fetch(other stages also) requires only one clock cycle. Number of cycles required to complete the given sequence of instructions are_____
Consider the following sequence of instructions Add #20,R0,R1 Mul #3,R2,R3 And #$3A,R2,R4 Add R0, R2, R5 In all instructions, the destination operand is given last. Init...
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1 votes
1 answer
251
Applied Test Series
Consider following assembly-language program: 1: MOV R3, R7 2: LOAD R8, (R3) 3: ADD R3, R3, 4 4: LOAD R9, (R3) 5: BNE R8, R9, L3 The sum of WAW, RAW, and WAR dependencies from the given code are_________
Consider following assembly-language program:1: MOV R3, R7 2: LOAD R8, (R3) 3: ADD R3, R3, 4 4: LOAD R9, (R3) 5: BNE R8, R9, L3The sum of WAW, RAW, and WAR dependencies f...
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254
Applied Gate Test Series
How to solve this?
How to solve this?
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2 answers
255
speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption
Which approach is correct?ASSIGNMENT LINK : https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdfnptel assignment q-1 Caption
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256
Test Series: COA
I need help in this one.
I need help in this one.
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257
COA Applied Course
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.
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1 votes
1 answer
258
APPLIED ROOTS Multisubject test
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cache (Set number in decimal) is the word from memory location ABCDE888 mapped?
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cach...
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0 votes
2 answers
260
Testbook Test Series
In designing a computer’s cache system,
In designing a computer’s cache system,
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