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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

2 votes
1 answer
2461
CO & Architecture
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. What percentage of time is the CPU in busy mode (approximately)?
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. What percentage of tim...
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0 votes
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2462
CO - BIT MANIPULATION INSTRUCTIONS
What is the purpose of having SHL & SHLA, when both perform the same operations. SHRA is useful in division of numbers in sign magnitude representation by any power of 2. But why is SHLA required?
What is the purpose of having SHL & SHLA, when both perform the same operations. SHRA is useful in division of numbers in sign magnitude representation by any power of 2....
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2 votes
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2464
question
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits).
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits).
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1 votes
1 answer
2465
Operand forwarding
given-13 my answer-12 plz verify. I0 IF ID OF PO WO I1 IF ID OF PO PO WO I2 IF ID OF PO WO I3 IF ID OF PO PO PO PO WO 1 2 3 4 5 6 7 8 9 10 11 12
given-13my answer-12plz verify.I0IFIDOFPOWO I1 IFIDOFPOPOWO I2 IFID OFPOWO I3 IFID OFPOPOPOPOWO 123456789101112
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4 votes
1 answer
2466
Control Unit
A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on an average requires 1 micro operation. What is the approximate size of control memory in bytes?
A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on an average r...
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0 votes
1 answer
2469
techtud
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address sp...
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4 votes
1 answer
2470
Pipelining
A 4-stage pipeline has the stage delay 100, 150, 170, 180 nanoseconds respectively. Registers that are used between the stages have a delay of 2 nanoseconds each. Assuming constant clock rate, the total time taken to process 520 data items on this pipeline will be ________ μs. (Upto 2 decimal places)
A 4-stage pipeline has the stage delay 100, 150, 170, 180 nanoseconds respectively. Registers that are used between the stages have a delay of 2 nanoseconds each. Assumin...
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5 votes
3 answers
2471
interrupt handling
Assume that memory is byte addressable with word size of 32 bits. The program has been loaded in memory 300(decimal) Address onwards. If an interrupt is occurred during the execution of HALT which is stored at 328. What will be the return Address pushed on to the stack?
Assume that memory is byte addressable with word size of 32 bits. The program has been loaded in memory 300(decimal) Address onwards. If an interrupt is occurred during t...
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2 votes
1 answer
2472
Minimum Register
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1 votes
0 answers
2474
gate2005
Is it possible to have vectored interrupt on processors with single interrupt request and grant line?
Is it possible to have vectored interrupt on processors with single interrupt request and grant line?
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0 votes
1 answer
2475
interrupt
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3 votes
1 answer
2476
2's complement
Is 2's complement code weighted or unweighted? Why?
Is 2's complement code weighted or unweighted? Why?
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1 votes
0 answers
2477
pipeLine
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1 votes
1 answer
2478
Pipeline
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1 votes
1 answer
2479
When content of Program counter is incremented?
The content of Program counter is incremented in which statge of execution of last instruction? Instruction Fetching Operand fetching Execution None of the above
The content of Program counter is incremented in which statge of execution of last instruction?Instruction FetchingOperand fetchingExecutionNone of the above
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0 votes
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2480
TEST_SERIES
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