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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

1 votes
1 answer
3362
pipeline speed up
consider unpipelined machine with 12 ns clock cycles. It uses 4 cycles for alu operation and branches, whereas 5 cycles for memory operations. Assume that the relative frequencies of these operations are 30% 20% 20%.Pipelining overhead is 1 ns. The speedup of the pipeline is: 2.0 3.1 2.8 3.5
consider unpipelined machine with 12 ns clock cycles. It uses 4 cycles for alu operation and branches, whereas 5 cycles for memory operations. Assume that the relative fr...
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3 votes
1 answer
3363
clash of cache block replacement and page replacement
can cache block replacement and page replacement activities clash with each other?
can cache block replacement and page replacement activities clash with each other?
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4 votes
1 answer
3364
cost per bit of the system
What will be the average cost per bit for a system with main memory of 1024 cost, 100 units and secondary memory of 4096 cost, 10 units? 35.7 28.0 82.0 none
What will be the average cost per bit for a system with main memory of 1024 cost, 100 units and secondary memory of 4096 cost, 10 units?35.7 28.0 82.0 none
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1 votes
4 answers
3365
Access Efficiency of a cache
Q. the access time of cache is 100 microsec, the access time of main memory is 900 microsec. and hit ratio is 95%, then what is the access efficiency related to cache? In this ques. what is meant by "access efficiency related to cache"? .
Q. the access time of cache is 100 microsec, the access time of main memory is 900 microsec. and hit ratio is 95%, then what is the access efficiency related to cache? In...
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1 votes
3 answers
3367
microinstruction
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4 votes
3 answers
3369
dma throughput
A DMA controller transfers $16$ bytes to memory using cycle stealing with frequency $1.2$GHz. The number of clock cycles used for transfer of $16$ bytes is $20$ Clock cycles. Find the throughout?
A DMA controller transfers $16$ bytes to memory using cycle stealing with frequency $1.2$GHz. The number of clock cycles used for transfer of $16$ bytes is $20$ Clock cyc...
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2 votes
2 answers
3372
Q7 ch-5 memory org.
Let cache of 0.7 hit having average access time 9 times faster than that of memory.  if average access time increases 40% from 80ns. What would be new hit ratio. A. 0.72     b. 0.36     c. 0.53     d. 0.80   My answer is 0.74   Am i correct?
Let cache of 0.7 hit having average access time 9 times faster than that of memory.  if average access time increases 40% from 80ns. What would be new hit ratio.A. 0.72 ...
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2 votes
1 answer
3375
Minimum and maximum (-ve) mantisa range in IEEE 754 32 bit
Minimum and maximum (-ve) mantisa range in IEEE 754 32 bit floating point number representation with 1bit for sign, 8 bit for exponent and 23 bit for mantisa.
Minimum and maximum (-ve) mantisa range in IEEE 754 32 bit floating point number representation with 1bit for sign, 8 bit for exponent and 23 bit for mantisa.
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1 votes
1 answer
3376
The number of bits (in binary) required to represent 25-digit decimal number
The number of bits (in binary) required to represent 25-digit decimal number
The number of bits (in binary) required to represent 25-digit decimal number
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1 votes
1 answer
3378
Made easy CA q16
How many 512k x 8 static RAM chips are needed to design the 2M x 32 memory module. a. 32 b. 8 c.16 d.64
How many 512k x 8 static RAM chips are needed to design the 2M x 32 memory module.a. 32 b. 8 c.16 d.64
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2 votes
3 answers
3379
Made easy CA q17
The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns.  what is the speed up? a.  2.9      b. 2.6       c. 3.2       d. 1.8
The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns.  what is the speed up?a.  2.9      ...
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3 votes
1 answer
3380
Pipeline q 18 CA
A nonpipeline system takes 50 ns to process a task. The same task can be processed in a six segment pipeline with a clock cycle of 10 ns.  determine the speed up ratio of the pipeline for 100 tasks.   a.  3.76     b. 4.76     c. 5.76     d. 2.76
A nonpipeline system takes 50 ns to process a task. The same task can be processed in a six segment pipeline with a clock cycle of 10 ns.  determine the speed up ratio o...
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