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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

2 votes
3 answers
3481
RAW dependencies
ADD R1 , R2, R2;  ADD R3, R2, R1; SUB R4, R1 , R5; ADD R3, R3, R4; FIND THE NUMBER OF READ AFTER WRITE(RAW) DEPENDENCIES IN THE ABOVE CODE.
ADD R1 , R2, R2; ADD R3, R2, R1;SUB R4, R1 , R5;ADD R3, R3, R4;FIND THE NUMBER OF READ AFTER WRITE(RAW) DEPENDENCIES IN THE ABOVE CODE.
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0 votes
2 answers
3483
A pipline p operation at 400Mhz has a speed up factor 6 and 70% efficiency. how many stages are there in pipieline??
Consider the following pseudo code. What is the total number of multiplications to be performed?D = 2 for i = 1 to n do for j = i to n do for k = j + 1 to n do D = D * 3�...
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1 votes
2 answers
3488
how many number of times the instruction sequence below will loop before coming out of the loop?
how many number of times the instruction sequence below will loop before coming out of the loop?              MOV AL,00H   A1:       INC AL              JNZ A1 a)1 b)256 c)255 d)will not come out of the loop
how many number of times the instruction sequence below will loop before coming out of the loop?             MOV AL,00H  A1:       INC AL      ...
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0 votes
2 answers
3492
mapping cache
Consider a cache with 64 blocks and  block size 16 bits block number of byte address 1600 is
Consider a cache with 64 blocks and  block size 16 bits block number of byte address 1600 is
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0 votes
1 answer
3493
variable instruction code
https://gateoverflow.in/?qa=blob&qa_blobid=256200031073543854
https://gateoverflow.in/?qa=blob&qa_blobid=256200031073543854
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1 votes
2 answers
3494
How many and what size of field exits in micro operation field?
If a micro program supports 46 micro operations with parallelism of 2, how many and what size of field exits in micro operation field? How do we get the size of micro-operation field as 9?
If a micro program supports 46 micro operations with parallelism of 2, how many and what size of field exits in micro operation field?How do we get the size of micro-oper...
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1 votes
1 answer
3496
Is stack pointer affected by conditional branch? If no, why?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructions, the maximum number of one address instructions are?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructi...
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6 votes
1 answer
3497
ISRO2014-10
The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is ______ $1$ $2$ $8$ $16$
The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is ______$1$$2$$8$$16$
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12 votes
5 answers
3498
ISRO2014-1
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for additional circuitry like buffering and decoding. $0$ $1$ $2$ $3$
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for addition...
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5 votes
2 answers
3499
Assume that 20 of the dynamic count of the total 100 instructions executed for a program are branch instructions.
Assume that 20 of the dynamic count of the total 100 instructions executed for a program are branch instructions. Delayed branching is used, with one delay slot. Assume t...
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