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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

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42
Classic RISC Pipeline
In which stage of the classic RISC pipeline, operand is fetched. Is it in Instruction Decode or Execute (ALU) stage?
In which stage of the classic RISC pipeline, operand is fetched. Is it in Instruction Decode or Execute (ALU) stage?
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43
ISRO 2024
The operation executed on data stored in registers is called Macro-operation Micro-operation Bit-operation Byte-operation
The operation executed on data stored in registers is calledMacro-operationMicro-operationBit-operationByte-operation
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44
ISRO 2024
An instruction pipeline can be implemented by means of LIFO buffer FIFO buffer Stack None of the above
An instruction pipeline can be implemented by means ofLIFO bufferFIFO bufferStackNone of the above
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46
Memory System
Design a memory system of capacity 2048x16 using 128x8 RAM chips. Show address lines, data lines, and control signals
Design a memory system of capacity 2048x16 using 128x8 RAM chips. Show address lines, data lines, and control signals
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52
#Applied Course
How I2-I4 is counted?
How I2-I4 is counted?
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53
RTMNU W22
Explain the difference between hardwired control unit and microprogrammed control unit with neat diagram. Illustrate the concept hardwired control associated with a control memory.
Explain the difference between hardwired control unit and microprogrammed control unit with neat diagram. Illustrate the concept hardwired control associated with a contr...
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57
Made Easy Test Series : Assume a system has a 64bit VAS and 48 bit PAS. Page size is equal to 4KB. If only single level paging is used then the size of the page table (in TB)
Can anybody explain why are they dividing the number of pages by page size?According to me, it should be – Page table size = Number of entries * entry sizei.e PT size =...
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60
gate 2024
do we have non linear pipelines and minimum average latency for gate cs 2024
do we have non linear pipelines and minimum average latency for gate cs 2024
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