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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&4&2&3&2&3&3&2&2.8&4
\\\hline\textbf{2 Marks Count}&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks}&8&6&3&10&7&3&\bf{3}&\bf{6.2}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in Digital Logic

1 vote
2 answers
1
is given ans correct ?
asked Aug 31 in Digital Logic Sanjay Sharma 250 views
0 votes
1 answer
2
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28 in Digital Logic Lakshman Patel RJIT 219 views
0 votes
1 answer
3
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28 in Digital Logic Lakshman Patel RJIT 110 views
0 votes
1 answer
4
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28 in Digital Logic Lakshman Patel RJIT 109 views
0 votes
0 answers
5
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28 in Digital Logic Lakshman Patel RJIT 65 views
0 votes
1 answer
6
0 votes
1 answer
7
A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required is $0$ $1$ $2$ $3$
asked Apr 2 in Digital Logic Lakshman Patel RJIT 78 views
0 votes
1 answer
8
If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by $nT$ sec $(n-1)T$ sec $n/T$ sec $(2n-1)T$ sec
asked Apr 2 in Digital Logic Lakshman Patel RJIT 51 views
0 votes
1 answer
9
If the input $\text{J}$ is connected through $\text{K}$ input of $\text{J-K}$, then flip-flop will behave as a D type flip-flop T type flip-flop S-R flip-flop Toggle switch
asked Apr 2 in Digital Logic Lakshman Patel RJIT 38 views
0 votes
1 answer
11
Which of the following conditions must be met to avoid race around problem? $\Delta t< t_{p}< T$ $T>\Delta t> t_{p}$ $2t_{p}< \Delta t< T$ none of these
asked Apr 2 in Digital Logic Lakshman Patel RJIT 40 views
0 votes
1 answer
12
0 votes
2 answers
13
0 votes
2 answers
14
1 vote
1 answer
15
0 votes
1 answer
16
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip-flops Clock input of one flip-flop
asked Apr 1 in Digital Logic Lakshman Patel RJIT 54 views
0 votes
2 answers
19
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip flops Clock input of one flip-flop
asked Apr 1 in Digital Logic Lakshman Patel RJIT 94 views
0 votes
1 answer
20
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