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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&3&2&4&2&3&2&3&3&2&2.6&4
\\\hline\textbf{2 Marks Count}&2&2&1&2&2&0&4&2&0&0&1.6&4
\\\hline\textbf{Total Marks}&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{6}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in Digital Logic

4 votes
3 answers
1
The format of the single-precision floating point representation of a real number as per the $\text{IEEE 754}$ ... $=00000000$ and mantissa $=0000000000000000000000001$ exponent $=00000001$ and mantissa $=0000000000000000000000000$ exponent $=00000001$ and mantissa $=0000000000000000000000001$
asked Feb 18 in Digital Logic Arjun 1.4k views
4 votes
4 answers
2
Which one of the following circuits implements the Boolean function given below? $f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.
asked Feb 18 in Digital Logic Arjun 1.1k views
5 votes
2 answers
3
7 votes
4 answers
4
If the numerical value of a $2$-byte unsigned integer on a little endian computer is $255$ more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer? $0\text{x}6665$ $0\text{x} 0001$ $0\text{x} 4243$ $0\text{x} 0100$
asked Feb 18 in Digital Logic Arjun 2.9k views
4 votes
2 answers
5
Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{lll} f(w,0,0,z) & = & 1 \\ f(1,x,1,z) & =& x+z \\ f(w,1,y,z) & = & wz +y \end{array}$The number of literals in the minimal sum-of-products expression of $f$ is _________
asked Feb 18 in Digital Logic Arjun 1.6k views
2 votes
4 answers
6
Let the representation of a number in base $3$ be $210$. What is the hexadecimal representation of the number? $15$ $21$ $\text{D}2$ $528$
asked Feb 18 in Digital Logic Arjun 869 views
2 votes
4 answers
7
Consider the following representation of a number in $\text{IEEE 754}$ single-precision floating point format with a bias of $127$.$S: 1\quad\quad E:\; 10000001\quad\quad F:\;11110000000000000000000$ Here $S, \;E$ and $F$ denote the ... components of the floating point representation. The decimal value corresponding to the above representation (rounded to $2$ decimal places) is ____________.
asked Feb 18 in Digital Logic Arjun 1.2k views
1 vote
3 answers
8
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$
asked Feb 18 in Digital Logic Arjun 837 views
4 votes
2 answers
9
Consider the following Boolean expression. $F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$ Which of the following Boolean expressions is/are equivalent to $\overline F$ (complement of $F$)? $(\overline X +\overline Y +\overline Z)(X+\overline Y)(Y+\overline Z)$ $X\overline Y + \overline Z$ $(X+\overline Z)(\overline Y +\overline Z)$ $X\overline Y +Y\overline Z + \overline X \overline Y \overline Z$
asked Feb 18 in Digital Logic Arjun 890 views
0 votes
1 answer
10
The period of a signal is $100$ ms, then the frequency of this signal in kilohertz is ______ $10$ $10^{-1}$ $10^{-2}$ $10^{-3}$
asked Nov 20, 2020 in Digital Logic jothee 279 views
0 votes
3 answers
11
Simplified expression/s for following Boolean function $F(A,B,C,D)=\Sigma(0,1,2,3,6,12,13,14,15)$ is/are $A’B’+AB+A’C’D’$ $A’B’+AB+A’CD’$ $A’B’+AB+BC’D’$ $A’B’+AB+BCD’$ Choose the correct answer from the options given below: $(a)$ only $(b)$ only $(a)$ and $(b)$ only $(b)$ and $(d)$ only
asked Nov 20, 2020 in Digital Logic jothee 367 views
1 vote
1 answer
12
is given ans correct ?
asked Aug 31, 2020 in Digital Logic Sanjay Sharma 540 views
1 vote
2 answers
13
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 2.3k views
0 votes
4 answers
14
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 368 views
0 votes
2 answers
15
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 326 views
0 votes
0 answers
16
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 201 views
0 votes
1 answer
17
1 vote
1 answer
18
A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required is $0$ $1$ $2$ $3$
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 387 views
0 votes
3 answers
19
If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by $nT$ sec $(n-1)T$ sec $n/T$ sec $(2n-1)T$ sec
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 515 views
0 votes
2 answers
20
If the input $\text{J}$ is connected through $\text{K}$ input of $\text{J-K}$, then flip-flop will behave as a D type flip-flop T type flip-flop S-R flip-flop Toggle switch
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 184 views
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