Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

Most answered questions in Digital Logic

40 votes

5 answers

101

GATE CSE 1996 | Question: 2.23
Consider the following state table for a sequential machine. The number of states in the minimized machine will be ... $4$ $3$ $2$ $1$

Consider the following state table for a sequential machine. The number of states in the minimized machine will be$$\begin{array}{|l|l|ll|}\hline \text{} & \text{} & \tex...

12.9k views

Kathleen asked Oct 9, 2014

43 votes

5 answers

102

GATE CSE 1996 | Question: 2.21
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output. Binary to Hex conversion Binary to BCD conversion Binary to Gray code conversion Binary to $radix-12$ conversion

Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output.Binary to Hex co...

14.0k views

Kathleen asked Oct 9, 2014

37 votes

5 answers

103

GATE CSE 1997 | Question: 2.5
An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator). The minimum addition time using the best architecture for this adder is proportional to $N$ proportional to $\log N$ a constant None of the above

An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator).The minimum addition ti...

9.6k views

Kathleen asked Sep 29, 2014

27 votes

5 answers

104

GATE CSE 2014 Set 3 | Question: 45
The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is $001, 010, 011$ $111, 110, 101$ $100, 110, 111$ $100, 011, 001$

The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycle...

17.6k views

go_editor asked Sep 28, 2014

36 votes

5 answers

105

GATE CSE 2014 Set 2 | Question: 45
The value of a $\text{float}$ type variable is represented using the single-precision $\text{32-bit}$ floating point format of $\text{IEEE-754}$ standard that uses $1$ $\text{bit}$ for sign, $\text{8 bits}$ for biased exponent and ... . The representation of $X$ in hexadecimal notation is $\text{C1640000H}$ $\text{416C0000H}$ $\text{41640000H}$ $\text{C16C0000H}$

The value of a $\text{float}$ type variable is represented using the single-precision $\text{32-bit}$ floating point format of $\text{IEEE-754}$ standard that uses $1$ $\...

11.2k views

go_editor asked Sep 28, 2014

25 votes

5 answers

106

GATE CSE 2012 | Question: 30
What is the minimal form of the Karnaugh map shown below? Assume that $X$ denotes a don’t care term $\bar{b} \bar{d}$ $ \bar { b } \bar { d } + \bar{b} \bar{c} $ $ \bar{b} \bar{d} + {a} \bar{b} \bar{c} {d}$ $ \bar{b} \bar{d} + \bar{b} \bar{c} + \bar{c} \bar{d} $

What is the minimal form of the Karnaugh map shown below? Assume that $X$ denotes a don’t care term $\bar{b} \bar{d}$$ \bar { b } \bar { d } + \bar{b} \bar{c} $$ \bar{b...

6.4k views

Arjun asked Sep 25, 2014

37 votes

5 answers

107

GATE CSE 1999 | Question: 2.9
Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function? XOR gates, NOT gates $2$ to $1$ multiplexers AND gates, XOR gates Three-input gates that output $(A.B) + C$ for the inputs $A, B$ and $C$.

Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function?XOR gates, NOT gates$2$ to $1$ multiplexersAND gates, XOR gatesT...

15.2k views

Kathleen asked Sep 23, 2014

19 votes

5 answers

108

GATE CSE 1999 | Question: 1.7
Which of the following expressions is not equivalent to $\bar{x}$? $x \text{ NAND } x$ $x \text{ NOR } x$ $x \text{ NAND } 1$ $x \text{ NOR } 1$

Which of the following expressions is not equivalent to $\bar{x}$?$x \text{ NAND } x$$x \text{ NOR } x$$x \text{ NAND } 1$$x \text{ NOR } 1$

8.6k views

Kathleen asked Sep 23, 2014

24 votes

5 answers

109

GATE CSE 2005 | Question: 16, ISRO2009-18, ISRO2015-2
The range of integers that can be represented by an $n$ bit $2’s$ complement number system is: $-2^{n-1} \text{ to } (2^{n-1} -1)$ $-(2^{n-1} -1) \text{ to } (2^{n-1} -1)$ $-2^{n-1} \text{ to } 2^{n-1}$ $-(2^{n-1} +1) \text{ to } (2^{n-1} -1)$

The range of integers that can be represented by an $n$ bit $2’s$ complement number system is:$-2^{n-1} \text{ to } (2^{n-1} -1)$$-(2^{n-1} -1) \text{ to } (2^{n-1} -1)...

9.7k views

Kathleen asked Sep 22, 2014

54 votes

5 answers

110

GATE CSE 2007 | Question: 48
Which of the following is TRUE about formulae in Conjunctive Normal Form? For any formula, there is a truth assignment for which at least half the clauses evaluate to true. For any formula, there is a truth assignment for which all the clauses ... formula such that for each truth assignment, at most one-fourth of the clauses evaluate to true. None of the above.

Which of the following is TRUE about formulae in Conjunctive Normal Form?For any formula, there is a truth assignment for which at least half the clauses evaluate to true...

14.9k views

Kathleen asked Sep 21, 2014

42 votes

5 answers

111

GATE CSE 2007 | Question: 33
Define the connective $*$ for the Boolean variables $X$ and $Y$ as: $X * Y = XY + X'Y'.$ Let $Z = X * Y$. Consider the following expressions $P$, $Q$ and $R$. $P : X = Y * Z, \\ Q :Y = X * Z, \\ R : X *Y * Z = 1$ Which of the following is TRUE? Only $P$ and $Q$ are valid. Only $Q$ and $R$ are valid. Only $P$ and $R$ are valid. All $P$, $Q$, $R$ are valid.

Define the connective $*$ for the Boolean variables $X$ and $Y$ as: $$X * Y = XY + X'Y'.$$ Let $Z = X * Y$. Consider the following expressions $P$, $Q$ and $R$.$$P : X = ...

8.9k views

Kathleen asked Sep 21, 2014

34 votes

5 answers

112

GATE CSE 2007 | Question: 8, ISRO2011-31
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates? $7$ $8$ $9$ $10$

How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates?$7$$8$$9$$10$

21.3k views

Kathleen asked Sep 21, 2014

27 votes

5 answers

113

GATE CSE 2004 | Question: 66
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is $1100 0100$ $1001 1100$ $1010 0101$ $1101 0101$

Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is$1100 0100$$1001 1100$$1010 0101$$1101 0101$

19.1k views

Kathleen asked Sep 18, 2014

44 votes

5 answers

114

GATE CSE 2004 | Question: 61
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below. To complete the circuit, the input $X$ should be $Q_2^c$ $Q_2 + Q_1$ $\left(Q_1 + Q_2\right)^c$ $Q_1 \oplus Q_2$

Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below.To complete the circuit, the input $X$ sh...

19.3k views

Kathleen asked Sep 18, 2014

26 votes

5 answers

115

GATE CSE 2004 | Question: 58
A circuit outputs a digit in the form of $4$ bits. $0$ is represented by $0000, 1$ by $0001, \ldots, 9$ by $1001$. A combinational circuit is to be designed which takes these $4$ bits as input and outputs $1$ if the digit $\geq$ $5$, and $0$ otherwise ... $\textsf{NOT}$ gates may be used, what is the minimum number of gates required? $2$ $3$ $4$ $5$

A circuit outputs a digit in the form of $4$ bits. $0$ is represented by $0000, 1$ by $0001, \ldots, 9$ by $1001$. A combinational circuit is to be designed which takes t...

11.9k views

Kathleen asked Sep 18, 2014

42 votes

5 answers

116

GATE CSE 2004 | Question: 28
What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding? $(113. + -111.) + 7.51$ $113. + (-111. + 7.51)$ $9.51$ and $10.0$ respectively $10.0$ and $9.51$ respectively $9.51$ and $9.51$ respectively $10.0$ and $10.0$ respectively

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding?$(113. + -111.) + 7.51$$113. + (-111. + 7.51)$$9....

16.2k views

Kathleen asked Sep 18, 2014

28 votes

5 answers

117

GATE CSE 2004 | Question: 17
A Boolean function $x’y’ + xy + x’y$ is equivalent to $x' + y'$ $x + y$ $x + y'$ $x' + y$

A Boolean function $x’y’ + xy + x’y$ is equivalent to$x' + y'$$x + y$$x + y'$$x' + y$

7.9k views

Kathleen asked Sep 18, 2014

53 votes

5 answers

118

GATE CSE 2003 | Question: 46
Consider the ALU shown below. If the operands are in $2's$ complement representation, which of the following operations can be performed by suitably setting the control lines $K$ and $C_0$ only (+ and - denote addition and subtraction respectively)? $A + B$, and $A - B$, but not $A + 1$ ... $A + B$, but not $A - B$ or $A + 1$ $A + B$, and $A - B$, and $A + 1$

Consider the ALU shown below. If the operands are in $2’s$ complement representation, which of the following operations can be performed by suitably setting the control...

16.8k views

Kathleen asked Sep 17, 2014

54 votes

5 answers

119

GATE CSE 2003 | Question: 44
A $\text{1-input}$, $\text{2-output}$ synchronous sequential circuit behaves as follows: Let $z_k, n_k$ denote the number of $0's$ and $1's$ respectively in initial $k$ bits of the input $(z_k+n_k=k)$. The circuit outputs $00$ until one of the ... is $01$. What is the minimum number of states required in the state transition graph of the above circuit? $5$ $6$ $7$ $8$

A $\text{1-input}$, $\text{2-output}$ synchronous sequential circuit behaves as follows:Let $z_k, n_k$ denote the number of $0’s$ and $1’s$ respectively in initial $k...

11.9k views

Kathleen asked Sep 17, 2014

28 votes

5 answers

120

GATE CSE 2003 | Question: 9
Assuming all numbers are in $2’s$ complement representation, which of the following numbers is divisible by $11111011$? $11100111$ $11100100$ $11010111$ $11011011$

Assuming all numbers are in $2’s$ complement representation, which of the following numbers is divisible by $11111011$?$11100111$$11100100$$11010111$$11011011$

10.4k views

Kathleen asked Sep 16, 2014

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