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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 1&2&3&2&4&2&3&2&3&3&1&2.5&4
\\\hline\textbf{2 Marks Count} & 2&2&2&1&2&2&0&4&2&0&0&1.7&4
\\\hline\textbf{Total Marks} & 5&6&7&4&8&6&3&10&7&3&\bf{3}&\bf{5.9}&\bf{10}\\\hline
\end{array}}}$$

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Most answered questions in Digital Logic

0 votes
4 answers
151
Gate 2018
Number System Question...What are all the options that can't be exactly represented...Question is like b7 b6 ....
Number System Question...What are all the options that can't be exactly represented...Question is like b7 b6 ....
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3 votes
4 answers
153
Gate CS 1996 Question no. 47
f implements, A) (ABC)' + A'BC' + ABC B) A + B + C C) A ⊕ B ⊕ C D) AB + BC + CA
f implements,A) (ABC)' + A'BC' + ABCB) A + B + CC) A ⊕ B ⊕ CD) AB + BC + CA
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0 votes
4 answers
154
Essential Prime Implicants
The number of essential prime implicates of F(A,B,C,D)=∑m(0,1,5,7,10,14,15)are
The number of essential prime implicates of F(A,B,C,D)=∑m(0,1,5,7,10,14,15)are
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9 votes
4 answers
155
ISRO2017-23
What is the minimum number of two-input $\text{NAND}$ gates used to perform the function of two-input $\text{OR}$ gate? One Two Three Four
What is the minimum number of two-input $\text{NAND}$ gates used to perform the function of two-input $\text{OR}$ gate?OneTwoThreeFour
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11 votes
4 answers
156
ISRO 2017-25
The 2-input XOR has a high output only when the input values are (a) low (b) high (c) same (d) different
The 2-input XOR has a high output only when the input values are(a) low(b) high(c) same(d) different
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9 votes
4 answers
157
ISRO2017-24
When two $n$-bit binary numbers are added the sum will contain at the most $n$ bits $n + 2$ bits $n + 3$ bits $n + 1$ bits
When two $n$-bit binary numbers are added the sum will contain at the most$n$ bits$n + 2$ bits$n + 3$ bits$n + 1$ bits
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3 votes
4 answers
158
Dout ###
How dual and complement different from each other
How dual and complement different from each other
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1 votes
4 answers
159
ISRO 2015 Truth table [EE]
The truth table X Y F 0 0 0 0 1 0 1 0 1 1 1 1 Represent the Boolean function (a) X (b) X - Y (c) X +Y (d) Y
The truth tableXYF000010101111 Represent the Boolean function(a) X(b) X - Y(c) X +Y(d) Y
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1 votes
4 answers
160
ISRO2014-ECE Digital logic
In the following circuit, Y can be expressed as : $\text{Y = BC + A}$ $\text{Y = AC}' + \text{BC}$ $\text{Y = C}$ $\text{Y = B}$
In the following circuit, Y can be expressed as :$\text{Y = BC + A}$$\text{Y = AC}' + \text{BC}$$\text{Y = C}$$\text{Y = B}$
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32 votes
4 answers
161
GATE CSE 2017 Set 2 | Question: 42
The next state table of a $2-$ ... $T_1 = Q_1+Q_0, \quad T_0= \bar{Q_1} \bar{Q_0}$ $T_1 = \bar{Q_1}Q_0, \quad T_0= Q_1 + Q_0$
The next state table of a $2-$bit saturating up-counter is given below.$\begin{array}{cc|cc} Q_1 & Q_0 & Q_1^+ & Q_0^+ \\ \hline 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0 \\ 1 & 0...
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7 votes
4 answers
165
GATE2017 EC Digital
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2 votes
4 answers
168
Test by Bikram | Digital Logic | Test 2 | Question: 16
Karnaugh map is used for the purpose of: Reducing the electronic circuits used. Mapping the given Boolean logic function. Minimizing the terms in a Boolean expression. Maximizing the terms of a given a Boolean expression.
Karnaugh map is used for the purpose of:Reducing the electronic circuits used.Mapping the given Boolean logic function.Minimizing the terms in a Boolean expression.Maximi...
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15 votes
4 answers
169
ME test
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of the MOD256 counter ? (in MHz)
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the...
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21 votes
4 answers
170
GATE CSE 1990 | Question: 1-iv-a
A $32$-bit floating-point number is represented by a $7$-bit signed exponent, and a $24$-bit fractional mantissa. The base of the scale factor is $16,$ The range of the exponent is ___________
A $32$-bit floating-point number is represented by a $7$-bit signed exponent, and a $24$-bit fractional mantissa. The base of the scale factor is $16,$The range of the ex...
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